PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 9

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

7.0
6.4
6.5
6.6
6.7
6.8
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
7.1
7.2
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
EXTENDED CAPABILITIES PARALLEL PORT (ECP) ........................................................... 119
6.4.1
6.4.2
6.4.3
ECP MODE REGISTERS ........................................................................................................ 120
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
6.5.12
6.5.13
6.5.14
6.5.15
6.5.16
6.5.17
6.5.18
6.5.19
DETAILED ECP MODE DESCRIPTIONS ............................................................................... 128
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
PARALLEL PORT REGISTER BITMAPS ............................................................................... 131
6.7.1
6.7.2
PARALLEL PORT PIN/SIGNAL LIST ...................................................................................... 134
FEATURES .............................................................................................................................. 135
FUNCTIONAL MODES OVERVIEW ....................................................................................... 135
7.2.1
7.2.2
EPP Data Register 1 (DATA1), Offset 05h ................................................................ 116
EPP Data Register 2 (DATA2), Offset 06h ................................................................ 116
EPP Data Register 3 (DATA3), Offset 07h ................................................................ 117
EPP Mode Transfer Operations ................................................................................ 117
EPP 1.7 and 1.9 Zero Wait State Data Write and Read Operations ......................... 118
ECP Modes ............................................................................................................... 119
Software Operation .................................................................................................... 119
Hardware Operation .................................................................................................. 119
Accessing the ECP Registers .................................................................................... 120
Second Level Offsets ................................................................................................ 120
ECP Data Register (DATAR), Bits 7-5 of ECR = 000 or 001, Offset 000h ................ 121
ECP Address FIFO (AFIFO) Register, Bits 7-5 of ECR = 011, Offset 000h .............. 121
ECP Status Register (DSR), Offset 001h .................................................................. 121
ECP Control Register (DCR), Offset 002h ................................................................ 122
Parallel Port Data FIFO (CFIFO) Register, Bits 7-5 of ECR = 010, Offset 400h ....... 122
ECP Data FIFO (DFIFO) Register, Bits 7-5 of ECR = 011, Offset 400h ................... 122
Test FIFO (TFIFO) Register, Bits 7-5 of ECR = 110, Offset 400h ............................. 123
Configuration Register A (CNFGA), Bits 7-5 of ECR = 111, Offset 400h .................. 123
Configuration Register B (CNFGB), Bits 7-5 of ECR = 111, Offset 401h .................. 123
Extended Control Register (ECR), Offset 402h ......................................................... 124
ECP Extended Index Register (EIR), Offset 403h ..................................................... 125
ECP Extended Data Register (EDR), Offset 404h .................................................... 126
ECP Extended Auxiliary Status Register (EAR), Offset 405h ................................... 126
Control0, Second Level Offset 00h ............................................................................ 126
Control2, Second Level Offset 02h ............................................................................ 126
Control4, Second Level Offset 04h ............................................................................ 127
PP Confg0, Second Level Offset 05h ........................................................................ 127
Software Controlled Data Transfer (Modes 000 and 001) ......................................... 128
Automatic Data Transfer (Modes 010 and 011) ........................................................ 128
Automatic Address and Data Transfers (Mode 100) ................................................. 130
FIFO Test Access (Mode 110) .................................................................................. 130
Configuration Registers Access (Mode 111) ............................................................. 130
Interrupt Generation .................................................................................................. 130
EPP Modes Parallel Port Register Bitmaps ............................................................... 131
ECP Modes Parallel Port Register Bitmaps .............................................................. 132
UART Modes: 16450 or 16550, and Extended .......................................................... 135
Sharp-IR, IrDA SIR Infrared Modes ........................................................................... 135
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