PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 216
PC87307VUL
Manufacturer Part Number
PC87307VUL
Description
PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
Manufacturer
National Semiconductor
Datasheet
1.PC87307VUL.pdf
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STR
TDR
THR
TFIFO
TSR
TV-Remote Mode
TXDR
TXFLV
UART
WDCF
WDST
WDTO
XDB
Status Register of the parallel port in SPP modes.
(Logical device 4, offset 01h.)
Tape Drive Register of the Floppy Disk Controller
(FDC). (Logical device 3, offset 03h.)
Transmitter Holding Register for UART1 write oper-
ations only. (Logical device 6, offset 00h, divisor
latch registers not accessible, bit 7 of LCR = 0.)
Test FIFO for the parallel port in Extended Capabili-
ties Port (ECP) mode 110. (Logical device 4, offset
400h.)
Internal Transmitter Shift Register for UART1.
See Consumer Remote Control mode.
Transmitter Data Register for write cycles for
UART2. (Logical device 5, bank 0, offset 00h.)
Transmission FIFO Level for UART2. (Logical de-
vices 5, bank 2, offset 06h.)
Universal Asynchronous Receiver Transmitter. The
part supports two UARTs, UART1 and UART2.
They are identical in UART modes; UART2 in-
cludes infrared and DMA support.
WATCHDOG Configuration register for Power Man-
agement module. (Logical device 8 at offset 06h.)
WATCHDOG Status register for Power Manage-
ment. (Logical device 8 at offset 07h.)
WATCHDOG Time-Out register for Power Manage-
ment. (Logical device 8 at offset 05h.)
X-Bus Data Buffer.
Glossary
216
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