PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 79

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

During DMA operations, FDC address signals are ignored
since AEN input signal is 1. The DACK signal acts as the
chip select signal for the FIFO, in this case, and the state of
the address lines A2-0 is ignored. The Terminal Count (TC)
signal can be asserted by the DMA controller to terminate
the data transfer at any time. Due to internal gating, TC is
only recognized when DACK is low.
PC-AT Drive Mode
In PC-AT drive mode when the FIFO is disabled, the con-
troller is in single byte transfer mode. That is, the system
has the time it takes to transfer one byte, to service a DMA
request (DRQ) from the controller. DRQ is deactivated be-
tween bytes.
PS/2 Drive Mode
In PS/2 drive mode, for DMA transfers with the FIFO dis-
abled, instead of single byte transfer mode, the FIFO is en-
abled with THRESH = 0Fh. Thus, DRQ is asserted when
one byte enters the FIFO during a read, and when one byte
can be written to the FIFO during a write. DRQ is deactivat-
ed by the leading edge of the DACK input signal, and is as-
serted again when DACK becomes inactive high. This
operation is very similar to burst mode transfer with the
FIFO enabled except that DRQ is deactivated between
bytes.
DMA Mode - FIFO Enabled
Read Data Transfers
Whenever the number of bytes in the FIFO is greater than
or equal to (16 THRESH), a DRQ is generated. This is the
trigger condition for the FIFO read data transfers from the
floppy controller to the microprocessor.
When the last byte in the FIFO has been read, DRQ be-
comes inactive. DRQ is asserted again when the FIFO trig-
ger condition is satisfied. After the last byte of a sector is
read from the disk, DRQ is again generated even if the FIFO
has not yet reached its threshold trigger condition. This
guarantees that all current sector bytes are read from the
FIFO before the next sector byte transfer begins.
Burst Mode Enabled - DRQ remains active until enough
Burst Mode Disabled - DRQ is deactivated after each
Write Data Transfers
Whenever the number of bytes in the FIFO is less than or
equal to THRESH, a DRQ is generated. This is the trigger
condition for the FIFO write data transfers from the micro-
processor to the FDC.
bytes have been read from the controller to empty the
FIFO.
read transfer. If the FIFO is not completely empty, DRQ
is asserted again after a 350 nsec delay. This allows
other higher priority DMA transfers to take place be-
tween floppy disk transfers.
In addition, this mode allows the controller to work cor-
rectly in systems where the DMA controller is put into a
read verify mode, where only DACK signals are sent to
the FDC, with no RD pulses. This read verify mode of
the DMA controller is used in some PC software. When
burst mode is disabled, a pulse from the DACK input
signal may be issued by the DMA controller, to correctly
clocks data from the FIFO.
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
79
Burst Mode Enabled - DRQ remains active until enough
Burst Mode Disabled - DRQ is deactivated after each
The FIFO has a byte counter which monitors the number of
bytes being transferred to the FIFO during write operations
whether burst mode is enabled or disabled. When the last
byte of a sector is transferred to the FIFO, DRQ is deacti-
vated even if the FIFO has not been completely filled. Thus,
the FIFO is cleared after each sector is written. Only after
the FDC has determined that another sector is to be written,
is DRQ asserted again. Also, since DRQ is deactivated im-
mediately after the last byte of a sector is written to the
FIFO, the system will not be delayed by deactivation of
DRQ and is free to do other operations.
Read and Write Data Transfers
The DACK input signal from the DMA controller may be held
active during an entire burst, or a pulse may be issued for
each byte transferred during a read or write operation. In
burst mode, the FDC deactivates DRQ as soon as it recog-
nizes that the last byte of a burst was transferred.
If a DACK pulse is issued for each byte, the leading edge of
this pulse is used to deactivate DRQ. If a DACK pulse is is-
sued, RD or WR is not required. This is the case during the
read-verify mode of the DMA controller.
If DACK is held active during the entire burst, the trailing
edge of the RD or WR pulse is used to deactivate DRQ.
DRQ is deactivated within 50 nsec of the leading edge of
DACK, RD, or WR. This quick response should prevent the
DMA controller from transferring extra bytes in most appli-
cations.
Overrun Errors
An overrun or underrun error terminates the execution of a
command, if the system does not transfer data within the al-
lotted data transfer time. (See Section 5.3.7 on page 76. )
This puts the controller in the result phase.
During a read overrun, the microprocessor is required to
read the remaining bytes of the sector before the controller
asserts the appropriate IRQ signifying the end of execution.
During a write operation, an underrun error terminates the
execution phase after the controller has written the remain-
ing bytes of the sector with the last correctly written byte to
the FIFO. Whether there is an error or not, an interrupt is
generated at the end of the execution phase, and is cleared
by reading the first result phase byte.
DACK asserted alone, without a RD or WR pulse, is also
counted as a transfer. If pulses of RD or WR are not being
issued for each byte, a DACK pulse must be issued for each
byte so that the Floppy Disk Controller(FDC) can count the
number of bytes correctly.
The VERIFY command, allows easy verification of data
written to the disk without actually transferring the data on
the data bus.
Interrupt Transfer Mode - FIFO Disabled
If interrupt transfer (non-DMA) mode is selected, the appro-
priate IRQ signal is asserted instead of DRQ, when each
byte is ready to be transferred.
bytes have been written to the controller to completely
fill the FIFO.
write transfer. If the FIFO is not full, DRQ is asserted
again after a 350 nsec delay. Deactivation of DRQ al-
lows other higher priority DMA transfers to take place
between floppy disk transfers.
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