PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 175

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

9.2.7
Hardware resets this register to 0Eh.
Bit 0 - Reserved
Bit 1 - Parallel Port Clock Enable
Bit 2 - UART2 Clock Enable
Bit 3 - UART1 Clock Enable
Bits 5,4 - Reserved
Bit 6 - UART2 Busy
0
7
This bit is reserved.
This bit is ANDed with bit 1 of the SuperI/O Parallel Port
Configuration register at index F0h of logical device 4. If
either bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0 - The clock is disabled.
1 - If bit 1 of the SuperI/O Parallel Port Configuration
This bit is ANDed with bit 1 of the SuperI/O UART2 Con-
figuration register at index F0h of logical device 5. If ei-
ther bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0 - The clock is disabled.
1 - If bit 1 of the SuperI/O UART2 Configuration regis-
This bit is ANDed with bit 1 of the SuperI/O UART1 Con-
figuration register at index F0h of logical device 6. If, ei-
ther bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0 - The clock is disabled.
1 - If bit 1 of the SuperI/O UART1 Configuration regis-
These bits are reserved.
When set to 1,this read-only bit indicates the UART2 is
busy. It is also accessed via the SuperI/O UART2 Con-
figuration register at index F0h of logical device 5. See
Section 2.8 on page 38.
UART1 busy
0
6
register is set to 1, the clock is enabled. (Default)
ter is set to 1, the clock is enabled. (Default)
ter is set to 1, the clock is enabled. (Default)
Power Management Control 3 Register (PMC3),
Index 04h
UART2 Busy
0
5
FIGURE 9-7. PMC3 Register Bitmap
0
4
Reserved
1
3
UART1 Clock Enable
1
2
UART2 Clock Enable
1
1
Parallel Port Clock Enable
0
0
Reset
Required
Reserved
Power Management
Control 3 Register
Power Management (Logical Device 8)
Index 04h
(PMC3)
175
Bit 7 - UART1 Busy
When set to 1,this read-only bit indicates the UART1 is
busy. It is also accessed via the SuperI/O UART2 Configu-
ration register at index F0h of logical device 6. See Section
2.9.1 on page 38.
9.2.8
This read/write register specifies the WATCHDOG time-out
period programmed by the user. It does not reflect the cur-
rent count while a countdown is in progress. The time-out
period may be from 1 to 255 minutes.
This register is cleared to 00h after reset. This register is
also reset to zero and disabled when the Power Manage-
ment device is activated.
See “The WATCHDOG Feature” on page 172 for more in-
formation.
Bits 7-0 - Programmed Time-Out Period
9.2.9
This register enables or masks the trigger events that re-
start the WATCHDOG timer.
When an enabled trigger event occurs, the programmed
time-out value (the value in the WDTO register) is reloaded
into the WATCHDOG timer. The WATCHDOG timer can
reach zero and activate WDO only if no trigger event occurs
for an entire time-out period.
Trigger events are not affected by the polarity or type of the
module interrupt.
0
7
These bits contain the programmed time-out period for
the WATCHDOG timer. They do not reflect the current
count while countdown is in progress.
Writing the value 00h resets the timer and deactivates
the WDO signal. Hardware reset clears the register to
00h, and deactivates the WATCHDOG timer function
and WDO. Software reset deactivates power manage-
ment (logical device 8) and resets the WATCHDOG tim-
er.
Values between 1 and 255 specify the countdown peri-
od, with one minute for each decrement.
When the timer reaches 00h, the WDO signal is enabled
(active low).
Writing a non-zero value to these bits resets the WDO
signal to 1 (inactive high).
0
6
Watchdog Time-Out (WDTO) Register,
Index 05h
WATCHDOG Configuration Register (WDCF),
Index 06h
FIGURE 9-8. WDTO Register Bitmap
0
5
0
4
0
3
Programmed Time-Out Period
0
2
0
1
0
0
Reset
Required
WATCHDOG Time-Out
Register (WDTO)
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Index 05h