PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 174

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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Bits 6-3 - Reserved
Bit 7 - GPIO Ports Function Enable
9.2.5
Hardware resets this read/write register to 00h.
A set bit puts the signals of the corresponding inactive logi-
cal device in TRI-STATE (except IRQ and DMA pins) re-
gardless of the value of bit 0 of the corresponding logical
device register at index F0h.
A cleared bit has no effect. In this case, the TRI-STATE sta-
tus of signals is controlled by bit 0 of the corresponding log-
ical device register at index F0h.
This is an OR function between PMC1 and the register at in-
dex F0h of the corresponding logical device.
Bits 2-0 - Reserved
Bit 3 - FDC TRI-STATE Control
Bit 4 - Parallel Port TRI-STATE Control
Bit 5 - UART2 and Infrared TRI-STATE Control
0
7
Reserved.
0 - GPIO Ports 1 and 2 are inactive (disabled). Reads
1 - GPIO Ports 1 and 2 are active (enabled) when bit 0
These bits are reserved.
0 - No effect. TRI-STATE controlled by bit 0 of the Su-
1 - FDC signals are in TRI-STATE.
0 - No effect. TRI-STATE controlled by bit 0 of the Su-
1 - Parallel Port signals are in TRI-STATE.
0 - No effect. TRI-STATE controlled by bit 0 of the Su-
1 - UART2 signals are in TRI-STATE.
Reserved
0
6
and writes are ignored; registers and pins are
maintained. Bit 0 of the Activate register (index
30h) of the GPIO Ports logical device is ignored.
(Default)
of the Activate register (index 30h) of the GPIO
Ports logical device is set.
perI/O FDC Configuration register. (Default)
See Section 2.6.1 on page 36.
perI/O Parallel Port Configuration register. (Default)
See Section 2.7.1 on page 37.
perI/O UART2 Configuration register. (Default)
See Section 2.8.1 on page 38.
Power Management Control 1 Register (PMC1),
Index 02h
UART1 TRI-STATE Control
0
5
FIGURE 9-5. PMC1 Register Bitmap
UART2 and Infrared TRI-STATE Control
0
4
Parallel Port TRI-STATE Control
0
3
FDC TRI-STATE Control
0
2
0
1
Reserved
0
0
Reset
Required
Power Management
Control 1 Register
Power Management (Logical Device 8)
Index 02h
(PMC1)
174
Bit 6 - UART1 TRI-STATE Control
Bit 7 - Reserved
9.2.6
Hardware resets this read/write register according to the
CFG2 and CFG3 strap pins, the status of the multiplier clock
and the hardware configuration. See Table 2-2 on page 25
and the description of the bits in this register.
Bits 1,0 - SuperI/O Clock Source
Bit 2 - Clock Multiplier Enable
Bits 6-3 - Reserved
Bit 7 - Valid Multiplier Clock Status
7
0 - No effect. TRI-STATE controlled by bit 0 of the Su-
1 - UART1 signals are in TRI-STATE.
Reserved.
Bit 0 is the Least Significant Bit (LSB).
00 - The 24 MHz clock is fed via the X1 pin.
01 - Reserved.
10 - The 48 MHz clock is fed via the X1 pin.
11 - The clock source is the on-chip clock multiplier.
0 - On-chip clock multiplier is disabled.
1 - On-chip clock multiplier is enabled.
These bits are reserved.
This bit is read only.
0 - On-chip clock (clock multiplier output) is frozen.
1 - On-chip clock (clock multiplier output) is stable and
Valid Multiplier Clock Status
0
6
perI/O UART1 Configuration register. (Default)
See Section 2.9.1 on page 38.
toggling.
Power Management Control 2 Register (PMC2),
Index 03h
0
5
FIGURE 9-6. PMC2 Register Bitmap
0
4
Reserved
0
3
X
2
Clock Multiplier Enable
X
1
X
0
SuperI/O Clock Source
Reset
Required
Power Management
Control 2 Register
Index 03h
(PMC2)