PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 144

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
Event Identification Register (EIR), Extended Mode
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
When this register is read the DMA event bit (bit 4) is
cleared if an 8237 type DMA is used. All other bits are
cleared when the corresponding interrupts are acknowl-
edged by reading the relevant register (e.g. reading MSR
clears MS_EV bit).
.
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
EIR Bits
0
3 2 1 0
0 0 0 1
0 1 1 0
0 1 0 0
1 1 0 0
0 0 0 0
FIGURE 7-9. EIR Register Bitmap, Extended Mode
7
0 0 1 0
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
Reserved
0
6
Reserved
0
5
TXEMP-EV or PLD_EV
Extended Mode, Read Cycles
0
Priority
4
Highest
Second
Second
Fourth
Level
Third
DMA_EV
0
-
3
MS_EV
0
2
LS_EV or TXHLT_EV
0
1
RX_FIFO Time-
Transmitter Low
Interrupt Type
Modem Status Any transition on CTS, DSR or DCD or
Receiver High
Link Status
TXLDL_EV
Data Level
Data Level
1
0
Event
Event
None
RXHDL_EV
Reset
Required
Out
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
TABLE 7-3. Non-Extended Mode Interrupt Priorities
Event Identification
Parity error, framing error, data overrun
or break event
Receiver Holding Register (RXD) full, or
RX_FIFO level equal to or above
threshold.
At least one character is in the
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
Transmitter Holding Register or
TX_FIFO empty.
a low to high transition on RI.
Register (EIR)
Offset 02h
Interrupt Set and Reset Functions
Bank 0,
Interrupt Source
144
None
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
Bit 2 - Link Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
Bit 3 - Modem Status Event (MS_EV)
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
In the UART, Sharp-IR and SIR modes, this bit is set to
1 when a receiver error or break condition is reported.
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
In the Consumer-IR mode, this bit indicates that a Link
Status Event (LS_EV) or a Transmitter Halted Event
(TXHLT_EV) occurred. It is set to 1 when any of the fol-
lowing conditions occurs:
— A receiver overrun.
— A transmitter underrun.
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
In any IR mode, the function of this bit depends on the
setting of the IRMSSL bit in the IRCR2 register (see Ta-
ble 7-4 and also “Bit 1 - MSR Register Function Select
in Infrared Mode (IRMSSL)” on page 158).
Read Link Status Register (LSR).
Reading the RXD or, RX_FIFO level
drops below threshold.
Reading the RXD port.
Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
Reading the Modem Status Register
(MSR).
Interrupt Reset Control
-