PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 152

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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7.11.13 Link Control Register (LCR) and Bank Select
These registers are the same as the registers at offset 03h
in bank 0.
7.12 BANK 2 – EXTENDED CONTROL AND STATUS
Bank 2 contains two alternate Baud Generator Divisor ports
and the Extended Control Registers (EXCR1 and EXCR2).
Register
EXCR1
EXCR2
IRCR1
7
7
MCR
REGISTERS
6
6
FIGURE 7-20. LBGD(H) Register Bitmap
FIGURE 7-19. LBGD(L) Register Bitmap
Register (BSR), Bank 1, Offset 03h
TABLE 7-12. Bits Cleared On Fallback
5
5
LOCK = x
Extended
0, 5 and 7
UART Mode & LOCK bit before Fallback
2 and 3
4
4
Mode
2 to 7
0 to 5
3
3
Most Significant Byte
2
2
Least Significant Byte
Legacy Baud Generator Divisor
Legacy Baud Generator Divisor
Non-Extended
1
1
of Baud Generator
LOCK = 0
of Baud Generator
5 and 7
0
0
Mode
0 to 5
none
none
Reset
Required
Reset
Required
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Non-Extended
High Byte port
Low Byte port
LOCK = 1
(LBGD(L))
Offset 00h
Offset 01h
Mode
(LBGD(H))
none
none
none
none
Bank 1,
Bank 1,
152
7.12.1 Baud Generator Divisor Ports, LSB (BGD(L))
These ports perform the same function as the Legacy Baud
Divisor Ports in Bank 1 and are accessed identically to them,
but do not change the operation mode of the module when ac-
cessed. Refer to Section 7.11.12 on page 151 for more detail.
Use these ports to set the baud rate when operating in Extend-
ed mode to avoid fallback to a Non-Extended operation mode,
i.e., 16550 compatible.When programming the baud rate, writ-
ing to BGDH causes the baud rate to change immediately.
Offset Register
00h
01h
02h
03h
04h
05h
06h
07h
x
x
7
7
x
x
6
6
LCR/BSR
FIGURE 7-22. BGD(H) Register Bitmap
FIGURE 7-21. BGD(L) Register Bitmap
and MSB (BGD(H)), Bank 2, Offsets 00h and 01h
BGD(H)
BGD(L)
EXCR1
EXCR2
RXFLV
TXFLV
Name
x
x
5
5
TABLE 7-13. Bank 2 Register Set
x
x
4
4
x
x
3
3
Baud Generator Divisor Port (Low byte)
Baud Generator Divisor Port (High byte)
Least Significant Byte
Most Significant Byte
x
x
2
2
Link Control/ Bank Select Register
Extended Control Register 1
Extended Control Register 2
x
x
1
1
of Baud Generator
of Baud Generator
x
x
Reserved
0
0
RX_FIFO Level
TX_FIFO Level
Reset
Required
Reset
Required
Baud Generator Divisor
Description
Baud Generator Divisor
High Byte Port
Low Byte Port
Offset 00h
Offset 01h
(BGD(H))
(BGD(L))
Bank 2,
Bank 2,