PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 137

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

The module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data in-
terchange with the system and composite serial data ex-
change with the external data channel, including:
The module supplies modem control registers, and a prior-
itized interrupt system for efficient interrupt handling.
7.4.1
The module defaults to 16450 mode after power up or reset.
UART 16550 mode is equivalent to 16450 mode, with the
addition of a 16-byte data FIFO for more efficient data I/O.
Transparent compatibility is maintained with this UART
mode in this module.
Despite the many additions to the basic UART hardware
and organization, the UART responds correctly to existing
software drivers with no software modification required.
When 16450 software initializes and addresses this mod-
ule, it will in always perform as a 16450 device.
Data transfer takes place by use of data buffers that inter-
face internally in parallel and with the external data channel
in a serial format. 16 or 32-byte data FIFOs may reduce
host overhead by enabling multiple-byte data transfers with-
in a single interrupt. With FIFOs disabled, this module is
equivalent to the standard 16450 UART. With FIFOs en-
abled, the hardware functions as a standard 16550 UART.
The composite serial data stream interfaces with the data
channel through signal conditioning circuitry such as
TTL/RS232 converters, modem tone generators, etc.
Data transfer is accompanied by software-generated con-
trol signals, which may be utilized to activate the communi-
cations channel and “handshake” with the remote device.
These may be supplied directly by the UART, or generated
by control interface circuits such as telephone dialing and
answering circuits, etc.
The composite serial data stream produced by the UART is
illustrated in Figure 7-2. A data word containing five to eight
bits is preceded by start bits and followed by an optional
parity bit and a stop bit. The data is clocked out, LSB first,
at a predetermined rate (the baud rate).
The data word length, parity bit option, number of start bits
and baud rate are programmable parameters.
The UART includes a programmable baud generator that
produces the baud rate clocks and associated timing sig-
nals for serial communication.
•
•
•
•
Format conversion between the internal parallel data
format and the external programmable composite seri-
al format. See Figure 7-2.
Serial data timing generation and recognition
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms
Status monitoring for all phases of the communica-
tions activity
START -LSB- DATA 5-8 -MSB- PARITY
16450 or 16550 UART Mode
FIGURE 7-2. Composite Serial Data
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
STOP
137
The system can monitor this module status at any time. Sta-
tus information includes the type and condition of the trans-
fer operation in process, as well as any error conditions
(e.g., parity, overrun, framing, or break interrupt).
The module resources include modem control capability
and a prioritized interrupt system. Interrupts can be pro-
grammed to match system requirements, minimizing the
CPU overhead required to handle the communications link.
Programmable Baud Generator
This module contains a programmable baud generator that
generates the clock rates for serial data communication
(both transmit and receive channels). It divides its input
clock by any divisor value from 1 to 2
frequency of the baud generator must be programmed to be
sixteen times the baud rate value. A 24 MHz input frequen-
cy is divided by a prescale value (PRESL field of EXCR2 -
see page 155. Its default value is 13) and by a 16-bit pro-
grammable divisor value contained in the Baud Generator
Divisor High and Low registers (BGD(H) and BGD(L) - see
page 152). Each divisor value yields a clock signal (BOUT)
and a further division by 16 produces the baud rate clock for
the serial data stream. It may also be output as a test signal
when enabled (see bit 7 of EXCR1 on page 154.)
These user-selectable parameters enable the user to gen-
erate a large choice of serial data rates, including all stan-
dard baud rates. A list of baud rates and their settings
appears in Table 7-14 on page 153.
Module Operation
Before module operation can begin, both the communica-
tions format and baud rate must be programmed by the soft-
ware. The communications format is programmed by
loading a control byte into the LCR register, while the baud
rate is selected by loading an appropriate value into the
baud generator divisor registers and the divisor preselect
values (PRESL) into EXCR2 (see page 155).
The software can read the status of the module at any time
during operation. The status information includes full or
empty state for both transmission and reception channels,
and any other condition detected on the received data
stream, like parity error, framing error, data overrun, or
break event.
7.4.2
In Extended UART mode of operation, the module configu-
ration changes and additional features become available
which enhance UART capabilities.
•
•
•
•
•
The interrupt sources are no longer prioritized; they
are presented bit-by-bit in the EIR (see page 143).
An auxiliary status and control register replaces the
scratchpad register. It contains additional status and
control flag bits (“Auxiliary Status and Control Register
(ASCR), Bank 0, Offset 07h” on page 150).
The TX_FIFO can generate interrupts when the num-
ber of outgoing bytes in the TX_FIFO drops below a
programmable threshold. In the Non-Extended UART
modes, only reception FIFOs have the thresholding
feature.
DMA capability is available.
Interrupts occur when the transmitter becomes empty
or a DMA event occurs.
Extended UART Mode
16
- 1. The output clock
www.national.com