PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 121

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

6.5.3
The ECP Data Register (DATAR) register is the same as
the DTR register (see Section 6.2.2), except that a read al-
ways returns the values of the PD7-0 signals instead of the
register latched data.
6.5.4
The ECP Address FIFO Register (AFIFO) is write only. In
the forward direction (when bit 5 of DCR is 0) a byte written
into this register is pushed into the FIFO and tagged as a
command.
Reading this register returns undefined contents. Writing to
this register in a backward direction (when bit 5 of DCR is 1)
has no effect and the data is ignored.
0
0
7
7
0
0
6
6
D7
A7
ECP Data Register (DATAR),
Bits 7-5 of ECR = 000 or 001, Offset 000h
ECP Address FIFO (AFIFO) Register,
Bits 7-5 of ECR = 011, Offset 000h
FIGURE 6-17. DATAR Register Bitmap
FIGURE 6-18. AFIFO Register Bitmap
0
0
5
5
D6
A6
0
0
4
4
D5
A5
Bits 7-5 of ECR = 000 or 001
0
0
3
3
D4
A4
Bits 7-5 of ECR = 011
0
0
2
2
D3
A3
0
0
Address Bits
1
Data Bits
1
D2
A2
0
0
0
0
D1
A1
Reset
Required
Reset
Required
D0
A0
ECP Address Register
ECP Data Register
Parallel Port (Logical Device 4)
Offset 000h
Offset 000h
(DATAR)
(AFIFO)
121
6.5.5
This read-only register displays device status. Writes to this
DSR have no effect and the data is ignored.
This register should not be confused with the DSR register
of the Floppy Disk Controller (FDC).
Bits 0 - EPP Time-Out Status
Bits 2,1 - Reserved
Bit 3 - ERR Status
Bit 4 - SLCT Status
Bit 5 - PE Status
Bit 6 - ACK Status
7
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the con-
stant value 1.
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when DSR is read.
In EPP modes:
0 - An EPP mode is set. No time-out occurred since
1 - Time-out occurred on EPP cycle (minimum of 10
These bits are reserved and are always 1.
This bit reflects the status of the ERR signal.
0 - Printer error.
1 - No printer error.
This bit reflects the status of the Select signal. The print-
er sets this signal high when it is online and selected
0 - Printer not selected. (Default)
1 - Printer selected and on-line.
This bit reflects the status of the Paper End (PE) signal.
0 - Paper not ended.
1 - No paper in printer.
This bit reflects the status of the ACK signal. This signal
is pulsed low after a character is received.
0 - Character received.
1 - No character received. (Default)
Printer Status
6
DSR was last read.
FIGURE 6-19. ECP DSR Register Bitmap
ECP Status Register (DSR), Offset 001h
sec). (Default)
ACK Status
5
PE Status
4
SLCT Status
3
ERR Status
1
1
2
1
1
Reserved
1
Reserved
1
0
Reset
Required
EPP Time-Out Status
ECP Status Register
Offset 001h
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(DSR)