PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 129

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Backward Direction (Bit 5 of DCR is 1)
When the ECP is in the backward direction, and the FIFO is
not full (bit 1 of ECR is 0), the ECP issues a read cycle to
the peripheral device and monitors the BUSY signal. If
BUSY is high the byte is a data byte and it is pushed into the
FIFO. If BUSY is low the byte is a command byte.
PD7-0
BUSY
ECP Mode
(ECR Bits)
7
0
0
0
0
1
1
1
1
AFD
STB
6
0
0
1
1
0
0
1
1
FIGURE 6-34. ECP Forward Write Cycle
5
0
1
0
1
0
1
0
1 Configuration CNFGA and CNFGB registers are accessible.
Parallel Port
ECP Mode
ECP FIFO The FIFO direction is automatic, i.e., controlled by bit 5 of DCR.
FIFO Test
Reserved
Standard
Name
FIFO
PS/2
EPP
Write cycles are under software control.
STB, AFD, INIT and SLIN are open-drain output signals.
Bit 5 of DCR is forced to 0 (forward direction) and PD7-0 are driven.
The FIFO is reset (empty).
Reading DATAR returns the last value written to DATAR.
Read and write cycles are under software control.
The FIFO is reset (empty).
STB, AFD, INIT and SLIN are push-pull output signals.
Write cycles are automatic, i.e., under hardware control (STB is controlled by hardware).
Bit 5 of DCR is forced to 0 internally (forward direction) and PD7-0 are driven.
STB, AFD, INIT and SLIN are push-pull output signals.
Read and write cycles to the device are controlled by hardware (STB and AFD are
controlled by hardware).
STB, AFD, INIT and SLIN are push-pull output signals.
EPP mode is enabled by bits 7 through 5 of the SuperI/O Parallel Port Configuration
register, as described in Section 2.7.1 on page 37.
In this mode, registers DATAR, DSR, and DCR are used as registers at offsets 00h, 01h
and 02h of the EPP instead of registers DTR, STR, and CTR.
STB, AFD, INIT, and SLIN are push-pull output buffers.
When there is no access to one of the EPP registers (ADDR, DATA0, DATA1, DATA2 or
DATA3), mode 100 behaves like mode 001, i.e., software can perform read and write
cycles. The software should check that bit 7 of the DSR is 1 before reading or writing the
DATAR register, to avoid corrupting an ongoing EPP cycle.
The FIFO is accessible via the TFIFO register.
The ECP does not issue ECP cycles to fill or empty the FIFO.
Parallel Port (Logical Device 4)
TABLE 6-11. ECP Modes
129
The ECP checks bit 7 of the command byte. If it is high the
byte is ignored, if it is low the byte is tagged as an RLC byte
(not pushed into the FIFO but used as a Run Length Count
to expand the next byte read). Following an RLC read the
ECP issues a read cycle from the peripheral device to read
the data byte to be expanded. This byte is considered a
data byte, regardless of its BUSY state (even if it is low).
This byte is pushed into the FIFO (RLC+1) times (e.g. for
RLC=0, push the byte once. For RLC=127 push the byte
128 times).
When the ECP is in the backward direction, and the FIFO is
not empty (bit 0 of ECR is 0), the FIFO can be emptied by
software reads from the FIFO register (true only for the
DFIFO in mode 011).
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to empty the
FIFO (only in mode 011).
Operation Description
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