PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 92

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
Result Phase
5.7.5
If an invalid command (illegal opcode byte in the command
phase) is received by the Floppy Disk Controller (FDC), the
controller responds with the result phase Status register 0
(ST0) in the result phase. See “Result Phase Status Regis-
ter 0 (ST0)” on page 81
The controller does not generate an interrupt during this
condition. Bits 7 and 6 in the MSR (see Section 5.3.6 page
75) are both set to 1, indicating to the microprocessor that
the controller is in the result phase and the contents of ST0
must be read.
Command Phase
Execution Phase
Result Phase
The system reads the value 80h from ST0 indicating that an
invalid command was received.
5.7.6
The LOCK command can be used to keep the FIFO en-
abled and to retain the values of some parameters after a
software reset.
After the command byte of the LOCK command is written,
its result byte must be read before the opcode of the next
command can be read. The LOCK command is not execut-
ed until its result byte is read by the microprocessor.
If the part is reset after the command byte of the LOCK com-
mand is written but before its result byte is read, then the
LOCK command is not executed. This prevents accidental
execution of the LOCK command.
7
7
7
None.
Result Phase Status Register 0 (STO) (80h)
The INVALID Command
The LOCK Command
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
6
6
6
5
5
5
Invalid Opcodes
Undefined
Undefined
Undefined
Undefined
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
92
Command Phase
Bit 7 - Control Reset Effect (LOCK)
Execution Phase
Result Phase
Bit 4 - Control Reset Effect (LOCK)
5.7.7
This command selects the special features of the controller.
The bits in the command bytes of the MODE command are
set to their default values after a hardware reset.
Command Phase
Second Command Phase Byte
Bit 0 - Extended Track Range (ETR)
LOCK
FWR
TMR
DENSEL
7
7
0
7
0
0
This bit determines how the FIFO, THRESH, and
PRETRK bits in the CONFIGURE command and, the
FWR, FRD, and BST bits in the MODE command are af-
fected by a software reset.
0 -Set default values after a software reset. (Default)
1 - Values are unaffected by a software reset.
Internal register is written.
Same as bit 7 of opcode in command phase.
This bit determines how the track number is stored. It is
cleared to 0 after a software reset.
0 - Track number is stored as a standard 8-bit value
1 - Track number is stored as a 12-bit value.
compatible with the IBM, ISO, and Toshiba Perpen-
dicular formats.
This allows access of up to 256 tracks during a
seek operation. (Default)
The upper four bits of the track value are stored in
the upper four bits of the head number in the sector
address field.
This allows access of up to 4096 tracks during a
seek operation. With this bit set, an extra byte is re-
quired in the SEEK command phase and SENSE
INTERRUPT result phase.
The MODE Command
FRD
IAF
6
0
6
0
6
0
0
BFR
BST
IPS
5
0
5
0
5
0
0
LOCK
R255
WLD
4
1
4
4
0
0
0
LOW PWR
3
0
3
0
3
0
0
0
Head Settle Factor
2
1
2
0
2
0
0
0
1
0
1
0
1
0
0
0
0
ETR
0
0
0
0
0
1
0
0