PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 145

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 4 - DMA Event Occurred (DMA_EV)
Bit 5 - Transmitter Empty (TXEMP_EV)
Bits 7,6 - Reserved
7.11.4 FIFO Control Register (FCR), Bank 0, Offset
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
Bit 0 - FIFO Enable (FIFO_EN)
Bit 1 - Receiver Soft Reset (RXSR)
Bit 2 - Transmitter Soft Reset (TXSR)
Bit 3 - Reserved
0
TABLE 7-4. Modem Status Event Detection Enable
7
IRMSSL Value
When an 8237 type DMA controller is used, this bit is set
to 1 when a DMA terminal count (TC) is signalled. It is
cleared upon read.
In UART, Sharp-IR and Consumer-IR modes, this bit is
the same as bit 6 of the LSR register. It is set to 1 when
the transmitter is empty.
Read/Write 0.
When set to 1 enables both the Transmision and Recep-
tion FIFOs. Resetting this bit clears both FIFOs.
In Consumer-IR modes the FIFOs are always enabled
and the setting of this bit is ignored.
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Read/Write 0.
Writing to this bit has no effect on the UART operation.
RXFTH1
0
6
02h
RXFTH0
0
1
0
5
FIGURE 7-10. FCR Register Bitmap
TXFTH1
0
4
TXFTH0
0
0
3
Modem Status Event (MS_EV)
Forced to 0.
Reserved
0
2
Write Cycles
TXSR
0
1
RXSR
0
0
Bit Function
Reset
Required
FIFO_EN
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Register (FCR)
FIFO Control
Offset 02h
Bank 0,
145
Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
7.11.5 Link Control Register (LCR), Bank 0, Offset
The Link Control Register (LCR) and the Bank Select Reg-
ister (BSR) (see the next register) share the same address.
The Link Control Register (LCR) selects the communica-
tions format for data transfers in UART, SIR and Sharp-IR
modes.
Upon reset, all bits are set to 0.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Link Control Register (SH_LCR) register in
bank 3 (See Section 7.13.2 on page 157). During a write op-
eration to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
Upon reset, all bits are set to 0.
•
•
TXFTH (Bits 5,4)
RXFTH (Bits 5,4)
In Non-Extended modes, these bits have no effect.
In Extended modes, these bits select the TX_FIFO in-
terrupt threshold level. An interrupt is generated when
the level of the data in the TX_FIFO drops below the en-
coded threshold.
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded thresh-
old.
If bit 7 is 0, the write affects both LCR and BSR.
If bit 7 is 1, and it is not one of the codes that selects
bank 1 (see Table 7-9, “Bank Selection Encoding” on
page 147), the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
00(Default)
00(Default)
03h, and Bank Selection Register (BSR),
All Banks, Offset 03h
01
10
11
01
10
11
TABLE 7-5. TX_FIFO Level Selection
TABLE 7-6. RX_FIFO Level Selection
RX_FIF0 Tresh.
TX_FIF0 Tresh.
(16 Levels)
(16 Levels)
14
1
4
8
13
1
3
9
RX_FIF0 Tresh.
TX_FIF0 Tresh.
(32 Levels)
(32 Levels)
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16
26
1
8
17
25
1
7