PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 155

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 5 - Enable Transmitter During Loopback (ETDLBK)
Bit 6 - Reserved
Bit 7 - Baud Generator Test (BTEST)
7.12.3 Link Control Register (LCR) and Bank Select
These registers are the same as the registers at offset 03h
in bank 0.
7.12.4 Extended Control and Status Register 2
This register configures the transmitter and receiver FIFOs,
and the baud generator prescaler.
Upon reset all bits are set to 0.
Bits 1,0 - TX_FIFO Size (TF_SIZ1,0)
Bits 3,2 - RX_FIFO Size (RF_SIZ1,0)
0
7
When this bit is set to 1, the transmitter serial output is en-
abled and functions normally when loopback is enabled.
Write 1.
When set, this bit routes the baud generator to the DTR
pin for testing purposes.
These bits select the number of levels for the TX_FIFO.
They are effective only when the FIFOs are enabled.
(See Table 7-16).
These bits select the number of levels for the RX_FIFO.
They are effective only when the FIFOs are enabled.
(See Table 7-17).
5. The modem status input pins (DSR, CTS, RI and DCD)
LOCK
0
0
6
are disconnected. The internal modem status signals,
are driven by the lower bits of the MCR register.
TF_SIZ1
Register (BSR), Bank 2, Offset 03h
(EXCR2), Bank 2, Offset 04h
FIGURE 7-25. EXCR2 Register Bitmap
TABLE 7-16. TX_FIFO Size Encoding
0
5
Reserved
0
0
1
0
PRESL1
4
PRESL0
0
3
0
2
RF_SIZ1
TF_SIZ0
0
1
RF_SIZ0
0
1
x
0
0
TF_SIZ1
Reset
Required
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
TF_SIZ0
Extended Control and
and Status Register 2
FIFO Depth
Reserved
16
32
Offset 04h
(EXCR2)
Bank 2,
155
Bits 5,4 - Prescaler Select
Bit 6 - Reserved
Read/write 0.
Bit 7 - Baud Divisor Register Lock (LOCK)
7.12.5 Reserved Register, Bank 2, Offset 05h
This register is reserved.
Bits 7-0 - Reserved
Read/write 0’s.
7.12.6 TX_FIFO Current Level Register (TXFLV),
This read-only register returns the number of bytes in the
TX_FIFO. It can be used to facilitate programmed I/O
modes during recovery from transmitter underrun in one of
the fast infrared modes.
The prescaler divides the 24 MHz input clock frequency
to provide the clock for the baud generator. (See Table
7-18).
When set to 1, accesses to the baud generator divisor
register through LBGD(L) and LBGD(H) as well as fall-
back are disabled from non-extended mode.
In this case two scratchpad registers overlaid with LB-
GD(L) and LBGD(H) are enabled, and any attempted
CPU access of the baud generator divisor register
through LBGD(L) and LBGD(H) will access the scratch-
pad registers instead. This bit must be set to 0 when ex-
tended mode is selected.
RF_SIZ1
Bank 2, Offset 06h
TABLE 7-17. RX_FIFO Size Encoding
Bit 5
0
0
1
0
0
1
1
TABLE 7-18. Prescaler Select
RF_SIZ0
Bit 4
0
1
x
0
1
0
1
Prescaler Value
FIFO Depth
Reserved
reserved
1.625
1.0
16
32
13
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