PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 173

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

9.2.2
This read/write register contains the data in the register
pointed to by the Power Management Index register at the
base address. See Figure 9-2.
9.2.3
Hardware resets this read/write register to FFh.
A set bit enables activation of the corresponding logical de-
vice via its Active register at index 30h.
A cleared bit disables the corresponding logical device re-
gardless of the value in its Active register. Bit 0 of the Active
register of a logical device is ignored when the correspond-
ing FER1 bit is cleared. See Figure 9-3.
Bit 0 - KBC Function Enable
Bit 1 - Reserved
Bit 2 - RTC Function Enable
0
1
7
7
0 - Disabled.
1 - Enabled. (Default)
Reserved.
0 - Disabled.
1 - Enabled. (Default)
FIGURE 9-2. Power Management Data Register
Reserved
0
1
6
6
Power Management Data Register,
Base Address + 01h
Function Enable Register 1 (FER1), Index 00h
UART1 Function Enable
0
1
5
5
FIGURE 9-3. FER1 Register Bitmap
UART2 and Infrared Function Enable
0
1
4
4
Parallel Port Function Enable
0
1
3
3
Data in the Indicated Power
Management Register
FDC Function Enable
0
1
2
2
RTC Function Enable
0
1
1
1
Bitmap
Reserved
0
1
0
0
Reset
Required
Reset
Required
KBC Function Enable
Power Management
Register 1 (FER1),
Function Enable
Power Management (Logical Device 8)
Data Register,
Base Address
Index 00h
+ 01h
173
Bit 3 - FDC Function Enable
Bit 4 - Parallel Port Function Enable
Bit 5 - UART2 and Infrared Function Enable
Bit 6 - UART1 Function Enable
Bit 7 - Reserved
9.2.4
Hardware resets this read/write register to FFh.
Bit 0 - Programmable CS0 Function Enable
Bit 1 - Programmable CS1 Function Enable
Bit 2 - Programmable CS2 Function Enable
1
7
0 - Disabled.
1 - Enabled. (Default)
0 - Disabled. (Default).
1 - Enabled.
0 - Disabled. (Default).
1 - Enabled.
0 - Disabled. (Default)
1 - Enabled.
Reserved.
See CS0 Configuration 0 register in Section 2.10.3 on
page 39.
0 - CS0 is disabled.CS0 is not asserted; CS0 configu-
1 - CS0 is enabled. (Default)
See CS1 Configuration 1 register in Section 2.10.7 on
page 40.
0 - CS1 is disabled.CS1 signal is not asserted, CS1
1 - CS1 is enabled. (Default)
See CS2 Configuration 2 register in Section 2.10.11 on
page 40.
0 - CS2 is disabled.The CS2 signal is not asserted,
1 - CS2 is enabled. (Default)
GPIO Ports Function Enable
1
6
ration and base address registers are maintained.
configuration and base address registers are main-
tained.
CS2 configuration and base address registers are
maintained.
Function Enable Register 2 (FER2), Index 01h
1
5
FIGURE 9-4. FER2 Register Bitmap
1
4
Reserved
1
3
1
2
Programmable CS2 Enable
1
1
Programmable CS1 Enable
1
0
Programmable CS0 Enable
Reset
Required
Register 2 (FER2),
Function Enable
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Index 01h