PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 139

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

comes active only if the frequency is within the programmed
range. Otherwise, the signal is ignored and no other action
is taken.
When the receiver enters the active state, the RXACT bit in
the ASCR register is set to 1. Once in the active state, the
receiver keeps sampling the infrared input signal and gen-
erates a bit string where a logic 1 indicates an idle condition
and a logic 0 indicates the presence of infrared energy. The
infrared input is sampled regardless of the presence of in-
frared pulses at a rate determined by the value loaded into
the baud generator divisor registers. The received bit string
is either de-serialized and assembled into 8-bit characters,
or it is converted to run-length encoded values. The result-
ing data bytes are then transferred into the RX_FIFO.
The receiver also sets the RXWDG bit in the ASCR register
each time an infrared pulse signal is detected. This bit is au-
tomatically cleared when the ASCR register is read, and it
is intended to assist the software in determining when the
infrared link has been idle for a certain time. The software
can then stop the data reception by writing a 1 into the RX-
ACT bit to clear it and return the receiver to the inactive
state.
The frequency bandwidth for the incoming modulated infra-
red signal is selected by the DFR and DBW fields in the IR-
RXDC register.
There are two Consumer-IR reception data modes: “Over-
sampled” and “Programmed T Period” mode. For either
mode the sampling rate is determined by the setting of the
baud generator divisor registers.
The “Over-sampled” mode can be used with the receiver
demodulator either enabled or disabled. It should be used
with the demodulator disabled when a detailed snapshot of
the incoming signal is needed, for example to determine the
period of the carrier signal. If the demodulator is enabled,
the stream of samples can be used to reconstruct the in-
coming bit string. To obtain good resolution, a fairly high
sampling rate should be selected.
The “Programmed-T-Period” mode should be used with the
receiver demodulator enabled. The T Period represents
one half bit time for protocols using biphase encoding, or
the basic unit of pulse distance for protocols using pulse dis-
tance encoding. The baud rate is usually programmed to
match the T Period. For long periods of logic low or high, the
receiver samples the demodulated signal at the pro-
grammed sampling rate.
Whenever a new infrared energy pulse is detected, the re-
ceiver synchronizes the sampling process to the incoming
signal timing. This reduces timing related errors and elimi-
nates the possibility of missing short infrared pulse se-
quences, especially with the RECS 80 protocol.
In addition, the “Programmed-T-Period” sampling minimiz-
es the amount of data used to represent the incoming infra-
red signal, therefore reducing the processing overhead in
the host CPU.
7.8 FIFO TIME-OUTS
Time-out mechanisms prevent received data from remain-
ing in the RX_FIFO indefinitely, if the programmed interrupt
or DMA thresholds are not reached.
An RX_FIFO time-out generates a Receiver Data Ready in-
terrupt and/or a receiver DMA request if bit 0 of IER and/or
bit 2 of MCR (in Extended mode) are set to 1 respectively.
An RX_FIFO time-out also sets bit 0 of ASCR to 1 if the
RX_FIFO is below the threshold. When a Receiver Data
Ready interrupt occurs, this bit is tested by the software to
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
139
determine whether a number of bytes indicated by the
RX_FIFO threshold can be read without checking bit 0 of
the LSR register.
The conditions that must exist for a time-out to occur in the
various modes of operation are described below.
When a time-out has occurred, it can only be reset when the
FIFO is read by the CPU or DMA controller.
7.8.1
Two timers (timer1 and timer 2) are used to generate two
different time-out events (A and B, respectively). Timer 1
times out after 64 sec. Timer 2 times out after four charac-
ter times.
Time-out event A generates an interrupt and sets the
RXF_TOUT bit (bit 0 of ASCR) when all of the following are
true:
Time-out event B activates the receiver DMA request and is
invisible to the software. It occurs when all of the following
are true:
7.8.2
The RX_FIFO time-out, in Consumer-IR mode, is disabled
while the receiver is active. It occurs when all of the follow-
ing are true:
7.8.3
This feature allows software to send high-speed data in Pro-
grammed Input/Output (PIO) mode without the risk of gen-
erating a transmitter underrun.
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission de-
ferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
that locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches either 14 for a 16-level
TX_FIFO, or 30 for a 32-level TX_FIFO, at which time the
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At least one byte is in the RX_FIFO, and
More than 64 sec or four character times, whichever is
greater, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
More than 64 sec or four character times, whichever is
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
At least one byte is in the RX_FIFO, and
More than 64 sec or four character times, whichever is
smaller, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
More than 64 sec or four character times, whichever is
smaller, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
At least one byte has been in the RX_FIFO for 64 sec
or more, and
The receiver has been inactive (RXACT = 0) for 64 sec
or more, and
More than 64 sec have elapsed since the last byte was
read from the RX_FIFO by the CPU or DMA controller.
UART, SIR or Sharp-IR Mode Time-Out
Conditions
Consumer-IR Mode Time-Out Conditions
Transmission Deferral
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