PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 3

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

— Software or hardware control
— 13 IRQ channel options
— Four 8-bit DMA channel options
— Demand mode DMA support
— An Enhanced Parallel Port (EPP) that is compatible
— An Enhanced Parallel Port (EPP) that also supports
— Support for an Enhanced Parallel Port (EPP) as
— An Extended Capabilities Port (ECP) that is IEEE
— Selection of internal pull-up or pull-down resistor for
— Reduction of PCI bus utilization by supporting a de-
— A protection circuit that prevents damage to the par-
— Output buffers that can sink and source14 mA
Three general purpose pins for three separate program-
mable chip select signals, as follows:
— Can be programmed for game port control
— The Chip Select 0 (CS0) signal produces open drain
— The Chip Select 1 (CS1) and 2 (CS2) signals have
— Decoding of chip select signals depends on the ad-
16 single-bit General Purpose I/O ports (GPIO):
— Modifiable addresses that are referenced by a 16-bit
— Programmable direction for each signal (input or
with the new version EPP 1.9, and is IEEE1284
compliant
version EPP 1.7 of the Xircom specification.
mode 4 of the Extended Capabilities Port (ECP)
1284 compliant, including level 2
Paper End (PE) pin
mand DMA mode mechanism and a DMA fairness
mechanism
allel port when a printer connected to it powers up or
is operated at high voltages
output and is powered by the V
push-pull buffers and are powered by the main V
dress and the Address Enable (AEN) signals, and
can be qualified using the Read (RD) and Write
(WR) signals.
programmable register
output) with configuration lock
CCH
Highlights
DD
3
— Programmable drive type for each output pin (open-
— Programmable option for internal pull-up resistor on
— A back-drive protection circuit
An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
Clock source options:
— Source is a 32.768 KHz crystal - an internal frequen-
— Source may be either a 48 MHz or 24 MHz clock in-
Enhanced Power Management (PM), including:
— Special configuration registers for power down
— WATCHDOG timer for power-saving strategies
— Reduced current leakage from pins
— Low-power CMOS technology
— Ability to shut off clocks to all modules
General features include:
— All accesses to the SuperI/O chip activate a Zero
— Access to all configuration registers is through an In-
— 160-pin Plastic Quad Flatpack (PQFP) package
drain or push-pull) with configuration lock
each input pin with configuration lock
cy multiplier generates all the required internal fre-
quencies.
put signal.
Wait State (ZWS) signal, except for accesses to the
Enhanced Parallel Port (EPP) and to configuration
registers
dex and a Data register, which can be relocated
within the ISA I/O address space
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