PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 112

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
6.2.1
In all Standard Parallel Port (SPP) modes, port operation is
controlled by the registers listed in Table 6-3.
All register bit assignments are compatible with the assign-
ments in existing SPP devices.
A single Data Register DTR is used for data input and out-
put (see Section 6.2.2). The direction of data flow is deter-
mined by the system setting in bit 5 of the Control Register
CTR.
Configuration at
Configuration at
Reconfiguration
Configuration
Initialization
Initialization
Run-Time
(Dynamic)
IRQ5,7
Signal
a. Section 2.7.1 on page 37 describes the bits of the SuperI/O Parallel Port configuration register.
b. See Section 6.5.12 on page 124
c. Before modifying this bit, set bit 4 of the SuperI/O Parallel Port configuration register at index F0h to 1.
d. Use bit 7 of the Control2 register at second level offset 2 of the parallel port to further specify compatibility. See
System
System
(Static)
SLIN
AFD
STB
INIT
Time
with
Section 6.5.17 on page 126.
Standard Parallel Port (SPP) Modes Register
Set
TABLE 6-2. Parallel Port Reset States
Reset Control
EPP Revision 1.7
EPP Revision 1.9
EPP Revision 1.7
EPP Revision 1.9
Operation Mode
SPP Compatible
SPP Compatible
SPP Extended
SPP Extended
MR
MR
MR
MR
MR
ECP(Default)
PP FIFO
State After Reset
TABLE 6-1. Parallel Port Mode Selection
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Configuration Register
SuperI/O Parallel Port
Zero
Parallel Port (Logical Device 4)
(Index F0h)
7 6 5
0 0 0
0 0 1
0 1 0
1 0 0
1 1 1
1 1 1
1 0 0
1 1 1
0 1 1
or
or
112
a
6.2.2
This bidirectional data port transfers 8-bit data in the direc-
tion determined by bit 5 of SPP register CTR at offset 02h
and mode.
The read or write operation is activated by the system RD
and WR strobes.
Table 6-4 tabulates DTR register operation.
TABLE 6-4. SPP DTR Register Read and Write Modes
Compatible
TABLE 6-3. Standard Parallel Port (SPP) Registers
Offset
00h
01h
02h
03h
Mode
SPP
Extended Control Register
(ECR) of the Parallel Port
SPP Data Register (DTR), Offset 00h
(Offset 402h)
Bit 5 of
Name
DTR
CTR
STR
CTR
7 6 5
0 0 0
0 1 0
0 0 1
1 0 0
0 1 1
x
x
-
-
-
-
RD WR
1
0
Description
b
Control
Status
0
1
Data
-
Data written to PD7-0.
of the Parallel Port
Control2 Register
Data read from the
(Offset 02h)
output latch
Result
4
0
1
TRI-STATE
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R
c
d
d
d
d
d
-
-
-
-
-