PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 120

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
6.5 ECP MODE REGISTERS
The ECP registers are each a byte wide, and are listed in
Table 6-6 in order of their offsets from the base address of
the parallel port. In addition, the ECP has control registers
at second level offsets, that are accessed via the EIR and
EDR registers. See Section 6.5.2 on page 120.
TABLE 6-6. Extended Capabilities Parallel Port (ECP)
Offset
000h
000h
001h
002h
400h
400h
400h
400h
401h
402h
403h
404h
405h
00h
02h
04h
05h
Control Registers at Second Level Offsets
CNFGA
CNFGB
Symbol
DATAR
AFIFO ECP Address FIFO
CFIFO
DFIFO
TFIFO
DSR
DCR
ECR
EDR
EAR
EIR
PP Confg0
Extended Auxiliary
Control0
Control2
Control4
Parallel Port Data
Parallel Port Data
Extended Control
Control Register
ECP Data FIFO
Extended Index
Status Register
Status Register
Extended Data
Configuration
Configuration
Description
Registers
Register A
Register B
Test FIFO
Register
Register
Register
Register
FIFO
(ECR Bits)
All Modes
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
Modes
7 6 5
0 0 0
0 0 1
0 1 1
0 1 0
0 1 1
1 1 0
1 1 1
1 1 1
Parallel Port (Logical Device 4)
R/W
R/W
R/W
R/W
W
W
R
R
R
120
6.5.1
The AFIFO, CFIFO, DFIFO and TFIFO registers access the
same ECP FIFO. The FIFO is accessed at Base + 000h, or
Base + 400h, depending on the mode field of ECR and the
register.
The FIFO can be accessed by system DMA cycles, as well
as system PIO cycles.
When the DMA is configured and enabled (bit 3 of ECR is 1
and bit 2 of ECR is 0) the ECP automatically (by hardware)
issues DMA requests to fill the FIFO (in the forward direc-
tion when bit 5 of DCR is 0) or to empty the FIFO (in the
backward direction when bit 5 of DCR is 1). All DMA trans-
fers are to or from these registers. The ECP does not assert
DMA requests for more than 32 consecutive DMA cycles.
The ECP stops requesting the DMA when TC is detected
during an ECP DMA cycle.
A “Demand DMA” feature reduces system overhead
caused by DMA data transfers. When this feature is en-
abled by bit 6 of the PP Config0 register at second level off-
set 05h, it prevents servicing of DMA requests until after
four have accumulated and are held pending. See “Bit 6 -
Demand DMA Enable” on page 128.
Writing into a full FIFO, and reading from an empty FIFO,
are ignored. The written data is lost, and the read data is un-
defined. The FIFO empty and full status bits are not affected
by such accesses.
Some registers are not accessible in all modes of operation,
or may be accessed in one direction only. Accessing a non
accessible register has no effect. Data read is undefined;
data written is ignored; and the FIFO does not update. The
SPP registers (DTR, STR and CTR) are not accessible
when the ECP is enabled.
To improve noise immunity in ECP cycles, the state ma-
chine does not examine the control handshake response
lines until the data has had time to switch.
In ECP modes:
6.5.2
The EIR, EDR, and EAR registers support enhanced con-
trol and status features. When bit 4 of the Parallel Port Con-
figuration register is 1 (as described in Section 2.7.1 on
page 37), EIR and EDR serve as index and data registers,
respectively.
EIR and EDR at offsets 403 and 404, respectively, access
the control registers (Control0, Control2, Control4 and PP
Config0) at second level offsets 00h, 02h, 04h and 05h, re-
spectively. These control registers are functional only. Ac-
cessing these registers is possible when bit 4 of the
SuperI/O Parallel Port Configuration register at index F0h of
logical device 4 is1 and when bit 2 or 10 of the base address
is 1.
•
•
•
DATAR replaces DTR of SPP/EPP
DSR replaces STR of SPP/EPP
DCR replaces CTR of SPP/EPP
Accessing the ECP Registers
Second Level Offsets