PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 165

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bits 2-0 - Reserved
Bit 3- ID/IRSL(2-1) Pins’ Direction Select (IRSL21_DS)
Bit 4 - IRRX Signal Invert (RXINV)
Bit 5 - ID0/IRSL0/IRRX2 Pin Direction Select (IRSL0_DS)
Bit 6 - Reserved
Bit 7 - Automatic Module Configuration (AMCFG)
Bit 5 of IRCFG4
Read/write 0.
This bit determines the direction of the ID/IRSL2 and
ID/IRSL1 pins.
0 - Pins’ direction is input.
1 - Pins’ direction is output.
This bit supports optical transceivers with receive signals
of opposite polarity (active high instead of active low).
When set to 1 an inverter is put on the path of the input
signal of the receiver.
This bit determines the direction of the ID0/
IRSL0/IRRX2 pin. See Table 7-31 on page 165.
0 - Pin’s direction is input.
1 - Pin’s direction is output.
Read/write 0.
When set to 1, this bit enables automatic infrared con-
figuration.
TABLE 7-31. Infrared Receiver Input Selection
(IRSL0_DS)
a. IRCFG4 is in bank 7, offset 07h. It is
b. AUX_IRRX (bit 4 of IRCR2) is described on
described on page 164.
page 158.
0
0
1
1
a
Bit 4 of IRCR2
(AUX_IRRX)
0
1
0
1
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
b
Selected IRRX
IRRX1
IRRX2
IRRX1
1
165
7.18 UART2 REGISTER WITH FAST IR REGISTER
0
7
0
7
7
7
Reserved
FEN1 - FIFO Enabled
BITMAPS
0
0
6
0
6
6
6
Reserved
FEN0 - FIFO Enabled
0
5
0
0
5
5
5
Non-Extended Modes, Read Cycles
TXEMP_IE
0
4
0
0
4
4
4
Reserved
DMA_IE
0
3
0
3
Reserved
3
3
Transmitted Data
MS_IE
RXFT - RX_FIFO Time-Out
0
2
0
Received Data
2
2
2
Extended Mode
Read Cycles
Write Cycles
LS_IE or TXUR_IE
0
1
0
IPR1 - Interrupt Priority 1
1
1
1
TXLDL_IE
0
IPR0 - Interrupt Priority 0
0
1
0
0
0
Reset
Required
Reset
Required
IPF - Interrupt Pending
Reset
Required
Reset
Required
RXHDL_IE
Event Identification
Transmitter Data
Interrupt Enable
Register (RXD)
Register (TXD)
Register (IER)
Receiver Data
Register (EIR)
Offset 01h
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Offset 00h
Offset 00h
Offset 02h
Bank 0,
Bank 0,
Bank 0,
Bank 0,