PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 37

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 0 - TRI-STATE Control
Bits 4-1 - Reserved
Bit 5 - DENSEL Polarity Control
Bit 6 - TDR Register Mode
Bit 7 - Four Drive Encode
2.6.2
This read/write register is reset by hardware to 00h. These
bits control bits 5 and 4 of the enhanced TDR register.
Bits 1,0 - Drive 0 ID
Bits 3,2 - Drive 1 ID
Bits 7-4 - Reserved
0
7
When set, this bit causes the FDC pins to be in TRI-
STATE (except the IRQ and DMA pins) when the FDC is
inactive (disabled).
This bit is ORed with a bit of PMC1 register of logical de-
vice 8.
0 - FDC pins are not put in TRI-STATE.
1 - FDC pins are put in TRI-STATE.
Reserved.
0 - DENSEL is active low for 500 Kbps or 1 Mbps data
1 - DENSEL is active high for 500 Kbps or 1 Mbps data
0 - AT Compatible TDR mode (bits 7 through 2 of TDR
1 - Enhanced TDR mode (bits 7 through 2 of TDR are
0 - Two floppy drives are directly controlled by DR1-0,
1 - Four floppy drives are controlled with the aid of an
These bits are reflected on bits 5 and 4, respectively, of
the Tape Drive Register (TDR) of the FDC when drive 0
is accessed. See Section 5.3.4 on page 73.
These bits are reflected on bits 5 and 4, respectively, of
the TDR register of the FDC when drive 1 is accessed.
See Section 5.3.4 on page 73.
These bits are reserved.
0
6
rates.
rates. (Default)
are not driven).
driven on TDR read).
MTR1-0.
external decoder.
FIGURE 2-10. Drive ID Register Bitmap
Drive ID Register, Index F1h
0
5
Reserved
0
4
0
3
0
2
Drive 1 ID
0
1
0
0
Drive 0 ID
Reset
Required
Drive ID Register,
Index F1h
Configuration
37
2.7 PARALLEL PORT CONFIGURATION REGISTER
2.7.1
This read/write register is reset by hardware to F2h. For nor-
mal operation and to maintain compatibility with future
chips, do not change bits 7 through 4.
Bit 0 - TRI-STATE Control
Bit 1 - Clock Enable
Bit 2 - Reserved
Bit 3 - Reported Parallel Port of PnP ISA Resource Data
Bit 4 - Configuration Bits within the Parallel Port
1
FIGURE 2-11. SuperI/O Parallel Port Configuration
7
When set, this bit causes the parallel port pins to be in
TRI-STATE (except IRQ and DMA pins) when the paral-
lel port is inactive (disabled). This bit is ORed with a bit
of the PMC1 register of logical device 8.
0 - Parallel port clock disabled.
1 - Parallel port clock enabled.
This bit is reserved.
Report to the ISA PnP Resource Data the device identi-
fication.
0 - ECP device.
1 - SPP device.
0 - The registers at base (address) + 403h, base +
1 - When ECP is selected by bits 7 through 5, the reg-
(LOGICAL DEVICE 4)
1
6
ECP modes and EPP time-out are not functional
when the logical device is active. Registers are
maintained.
All operation modes are functional when the logical
device is active. This bit is ANDed with a bit of the
PMC3 register of the power management device
(logical device 8).
404h and base + 405h are not accessible (reads
and writes are ignored).
isters at base (address) + 403h, base + 404h and
base + 405h are accessible.
SuperI/O Parallel Port Configuration Register,
Index F0h
1
5
Parallel Port Mode Select
1
4
Configuration Bits within the Parallel Port
0
3
Register Bitmap
PP of PnP ISA Resource Data
0
2
Reserved
1
1
Clock Enable
0
0
Reset
Required
TRI-STATE Control
Configuration Register,
SuperI/O Parallel Port
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Index F0h