HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 102
HD6412320
Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412320.pdf
(1302 pages)
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Section 2 CPU
2.8.4
In this state the CPU executes program instructions in sequence.
2.8.5
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts.
There is one other bus master in addition to the CPU: the DMA controller (DMAC) * and data
transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
Note: * The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 72 of 1268
REJ09B0220-0600
Advanced mode
SP
Program Execution State
Bus-Released State
Note: * Ignored when returning.
(c) Interrupt control mode 0
Figure 2.13 Stack Structure after Exception Handling (Examples)
(24 bits)
CCR
PC
SP
(d) Interrupt control mode 2
Reserved*
(24 bits)
CCR
EXR
PC
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