HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 948

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 20 Clock Pulse Generator
20.4
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
20.5
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
20.6
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
Rev.6.00 Sep. 27, 2007 Page 918 of 1268
REJ09B0220-0600
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit

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