HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 909

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 ROM
Following the elapse of (x) µs or more after the SWEn bit is set to 1 in flash memory control
register n (FLMCRn), 128-byte program data is stored in the program data area and reprogram
data area, and the 128-byte data in the reprogram data area is written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive
byte data transfers are performed. The program address and program data are latched in the flash
memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this
case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation
for program mode (program setup) is carried out by setting the PSUn bit in FLMCRn, and after
the elapse of (y) µs or more, the operating mode is switched to program mode by setting the Pn bit
in FLMCRn. The time during which the Pn bit is set is the flash memory programming time. Set
the programming time according to the table in the programming flowchart.
19.25.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for
addresses H'040000 to H'07FFFF)
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the Pn bit in
FLMCRn is cleared to 0, then the PSUn bit is cleared to 0 at least (α) µs later). Next, the
watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to
program-verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode,
a dummy write of H'FF data should be made to the addresses to be read. The dummy write should
be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify
data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the
dummy write before performing this read operation. Next, the originally written data is compared
with the verify data, and reprogram data is computed (see figure 19.70) and transferred to the
reprogram data area. After 128 bytes of data have been verified, exit program-verify mode and
wait for at least (η) µs, then clear the SWEn bit in FLMCRn to 0, and wait again for at least (θ)
μs. If reprogramming is necessary, set program mode again, and repeat the program/program-
verify sequence as before. However, ensure that the program/program-verify sequence is not
repeated more than (N) times on the same bits.
Rev.6.00 Sep. 27, 2007 Page 879 of 1268
REJ09B0220-0600