HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 1138

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix B Internal I/O Registers
BCRL—Bus Control Register L
Rev.6.00 Sep. 27, 2007 Page 1108 of 1268
REJ09B0220-0600
Bit
Initial value
Read/Write
:
:
:
BRLE
R/W
Bus Release Enable
7
0
0
1
Note: * The BREQO output pin can be switched between
External bus release disabled
External bus release enabled
BREQO Pin Enable
0
1
BREQOE
R/W
6
0
BREQO output disabled
BREQO * output enabled
PF
2
and P5
External Addresses H'010000 to H'03FFFF Enable
Notes: 1. Do not access a reserved area.
0
1
EAE
R/W
5
1
3
• In the H8S/2329B, H8S/2328
• In the H8S/2327, addresses H'010000 to H'01FFFF are on-chip ROM,
• In the H8S/2323, addresses H'010000 to H'03FFFF are a reserved area
Addresses H'010000 to H'03FFFF
in external expanded mode or reserved area
by means of BREQOPS.
2. Address H'010000 to H'03FFFF in the H8S/2328.
3. H8S/2328B in flash memory version.
H'03FFFF
and addresses H'020000 to H'03FFFF are a reserved area
Address H'010000 to H'05FFFF in the H8S/2329B.
Address H'010000 to H'07FFFF in the H8S/2326.
Reserved
Only 1 should be written to this bit
R/W
—
4
1
*2
are on-chip ROM
DACK Timing Select
Note: In the H8S/2321 this bit is reserved and should only
0
1
DDS
R/W
3
1
H'FED5
When DMAC single address transfer is performed in
DRAM space, full access is always executed. DACK
signal goes low from Tr or T1 cycle
Burst access is possible when DMAC single address
transfer is performed in DRAM space. DACK signal
goes low from Tc1 or T2 cycle
be written with 1.
Reserved
Only 1 should be written to this bit
R/W
*3
—
2
1
, and H8S/2326, addresses H'010000 to
*2
are external addresses
Write Data Buffer Enable
WDBE
0
1
R/W
*2
1
0
in single-chip mode
Write data buffer function
not used
Write data buffer function
used
WAIT Pin Enable
Note: * The WAIT input pin
0
1
WAITE
Wait input by WAIT
pin * disabled
Wait input by WAIT
pin * enabled
R/W
can be switched
between PF
P5
WAITPS.
0
0
3
Bus Controller
*1
by means of
2
and
*1