HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 235

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
φ
Figure 6.33 Relationship between Chip Select (CS) and Read (RD)
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
Address bus
CS (area A)
CS (area B)
Rev.6.00 Sep. 27, 2007 Page 205 of 1268
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
T
(ICIS1 = 1 (initial value))
2
Section 6 Bus Controller
T
3
REJ09B0220-0600
T
I
Bus cycle B
T
1
T
2