HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 1200

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix B Internal I/O Registers
SSR1—Serial Status Register 1
Rev.6.00 Sep. 27, 2007 Page 1170 of 1268
REJ09B0220-0600
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
:
:
:
Note: 1. The DMAC is not supported in the H8S/2321.
Transmit Data Register Empty
0
1
R/(W)*
TDRE
7
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Note: 1. The DMAC is not supported in the H8S/2321.
Receive Data Register Full
R/(W)*
0
1
RDRF
6
0
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC
[Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
Overrun Error
R/(W)*
ORER
0
1
*1
5
0
or DTC is activated by a TXI interrupt and writes data to TDR
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Framing Error
0
1
R/(W)*
FER
4
0
*1
[Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks the stop bit at the end of the receive
data when reception ends, and the stop bit is 0
Parity Error
or DTC is activated by an RXI interrupt and reads data from RDR
0
1
R/(W)*
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
PER
3
0
TEND
Transmit End
Note: 1. The DMAC is not supported in the H8S/2321.
0
1
R
2
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-byte
and writes data to TDR
Multiprocessor Bit
serial transmit character
0
1
MPB
H'FF84
R
1
0
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Multiprocessor Bit Transfer
0
1
MPBT
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
*1
or DTC is activated by a TXI interrupt
SCI1