HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 16

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3
7.4
7.5
7.6
7.7
Section 8 Data Transfer Controller....................................................................311
8.1
8.2
Rev.6.00 Sep. 27, 2007 Page xvi of xxx
REJ09B0220-0600
7.2.4
7.2.5
Register Descriptions (2) (Full Address Mode) ................................................................ 237
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions (3) .................................................................................................. 250
7.4.1
7.4.2
7.4.3
Operation........................................................................................................................... 255
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 283
7.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 291
7.5.12 Write Data Buffer Function ................................................................................. 297
7.5.13 DMAC Multi-Channel Operation ........................................................................ 298
7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles,
7.5.15 NMI Interrupts and DMAC.................................................................................. 301
7.5.16 Forced Termination of DMAC Operation............................................................ 302
7.5.17 Clearing Full Address Mode ................................................................................ 303
Interrupts ........................................................................................................................... 304
Usage Notes ...................................................................................................................... 305
Overview........................................................................................................................... 311
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 314
DMA Control Register (DMACR) ...................................................................... 227
DMA Band Control Register (DMABCR) .......................................................... 231
Memory Address Register (MAR)....................................................................... 237
I/O Address Register (IOAR) .............................................................................. 237
Execute Transfer Count Register (ETCR) ........................................................... 238
DMA Control Register (DMACR) ...................................................................... 240
DMA Band Control Register (DMABCR) .......................................................... 244
DMA Write Enable Register (DMAWER) .......................................................... 250
DMA Terminal Control Register (DMATCR)..................................................... 253
Module Stop Control Register (MSTPCR) .......................................................... 254
Transfer Modes .................................................................................................... 255
Sequential Mode .................................................................................................. 257
Idle Mode............................................................................................................. 260
Repeat Mode ........................................................................................................ 263
Single Address Mode........................................................................................... 267
Normal Mode....................................................................................................... 270
Block Transfer Mode ........................................................................................... 273
DMAC Activation Sources .................................................................................. 279
Basic DMAC Bus Cycles..................................................................................... 282
and the DTC......................................................................................................... 300
Features................................................................................................................ 311
Block Diagram ..................................................................................................... 312
Register Configuration......................................................................................... 313