HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 288

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (Not Supported in the H8S/2321)
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Figure 7.3 illustrates operation in sequential mode.
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Rev.6.00 Sep. 27, 2007 Page 258 of 1268
REJ09B0220-0600
Address T
Address B
Figure 7.3 Operation in Sequential Mode
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)
Where : L = Value set in MAR
N = Value set in ETCR
DTID
· (2
DTSZ
· (N–1))
IOAR