HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 234

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 6.32 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Rev.6.00 Sep. 27, 2007 Page 204 of 1268
REJ09B0220-0600
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS0 = 0)
T
2
Figure 6.32 Example of Idle Cycle Operation (2)
T
floating time
Long output
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
T
(b) Idle cycle inserted
1
Bus cycle A
(ICIS0 = 1 (initial value))
T
2
T
3
T
I
Bus cycle B
T
1
T
2