HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 14

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.6
Section 6 Bus Controller....................................................................................143
6.1
6.2
6.3
6.4
6.5
Rev.6.00 Sep. 27, 2007 Page xiv of xxx
REJ09B0220-0600
DTC and DMAC Activation by Interrupt ......................................................................... 139
5.6.1
5.6.2
5.6.3
Overview........................................................................................................................... 143
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 149
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Overview of Bus Control .................................................................................................. 165
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Basic Bus Interface ........................................................................................................... 170
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
DRAM Interface (Not supported in the H8S/2321) .......................................................... 183
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
Overview.............................................................................................................. 139
Block Diagram ..................................................................................................... 140
Operation ............................................................................................................. 141
Features................................................................................................................ 143
Block Diagram ..................................................................................................... 145
Pin Configuration................................................................................................. 146
Register Configuration......................................................................................... 148
Bus Width Control Register (ABWCR)............................................................... 149
Access State Control Register (ASTCR) ............................................................. 150
Wait Control Registers H and L (WCRH, WCRL).............................................. 151
Bus Control Register H (BCRH) ......................................................................... 154
Bus Control Register L (BCRL) .......................................................................... 157
Memory Control Register (MCR)........................................................................ 159
DRAM Control Register (DRAMCR) ................................................................. 162
Refresh Timer Counter (RTCNT)........................................................................ 164
Refresh Time Constant Register (RTCOR) ......................................................... 164
Area Partitioning.................................................................................................. 165
Bus Specifications................................................................................................ 166
Memory Interfaces ............................................................................................... 167
Advanced Mode ................................................................................................... 168
Chip Select Signals .............................................................................................. 169
Overview.............................................................................................................. 170
Data Size and Data Alignment............................................................................. 170
Valid Strobes........................................................................................................ 172
Basic Timing........................................................................................................ 173
Wait Control ........................................................................................................ 181
Overview.............................................................................................................. 183
Setting DRAM Space........................................................................................... 183
Address Multiplexing........................................................................................... 184
Data Bus............................................................................................................... 184
Pins Used for DRAM Interface............................................................................ 185
Basic Timing........................................................................................................ 186