HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 344

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 8 Data Transfer Controller
8.2
8.2.1
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
Rev.6.00 Sep. 27, 2007 Page 314 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
Register Descriptions
DTC Mode Register A (MRA)
Bit 6
SM0
0
1
Bit 4
DM0
0
1
:
:
Unde-
fined
SM1
7
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Unde-
fined
SM0
6
Unde-
fined
DM1
5
Unde-
fined
DM0
4
Unde-
MD1
fined
3
Unde-
fined
MD0
2
Unde-
fined
DTS
1
Unde-
fined
Sz
0

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