HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 342

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 8 Data Transfer Controller
8.1.2
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM * . A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Rev.6.00 Sep. 27, 2007 Page 312 of 1268
REJ09B0220-0600
Interrupt
request
Block Diagram
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERF
DTVECR
Interrupt controller
CPU interrupt
request
Figure 8.1 Block Diagram of DTC
: DTC mode registers A and B
: DTC transfer count registers A and B
: DTC source address register
: DTC destination address register
: DTC enable registers A to F
: DTC vector register
DTC
Internal address bus
Internal data bus
On-chip
RAM

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