HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 131

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4.1
4.1.1
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1
Priority
High
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in the program
Overview
Exception Handling Types and Priority
Exception Type
Reset
Trace *
Interrupt
Trap instruction (TRAPA) *
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
1
Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the
RES pin, or when the watchdog timer overflows.
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued *
Started by execution of a trap instruction (TRAPA)
2
Rev.6.00 Sep. 27, 2007 Page 101 of 1268
Section 4 Exception Handling
REJ09B0220-0600