MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
High-performance, Low-power AVR
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 16K Bytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1K Byte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels in TQFP Package Only
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V for ATmega16A
Speed Grades
– 0 - 16 MHz for ATmega16A
Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16A
– Active: 0.6 mA
– Idle Mode: 0.2 mA
– Power-down Mode: < 1µA
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega16A
8154B–AVR–07/09

ATMEGA16A-PU Summary of contents

  • Page 1

    ... PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega16A • Speed Grades – MHz for ATmega16A • Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16A – Active: 0.6 mA – Idle Mode: 0.2 mA – Power-down Mode: < 1µA ® 8-bit Microcontroller (1) 8-bit ...

  • Page 2

    ... Pin Configurations Figure 1-1. ATmega16A 2 Pinout ATmega16A PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 ...

  • Page 3

    ... Overview The ATmega16A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 8154B–AVR–07/09 ...

  • Page 4

    ... Block Diagram Figure 2-1. VCC GND AVCC AREF ATmega16A 4 Block Diagram PA0 - PA7 PORTA DRIVERS/BUFFERS PORTA DIGITAL INTERFACE MUX & ADC INTERFACE ADC PROGRAM STACK COUNTER POINTER PROGRAM SRAM FLASH INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS X INSTRUCTION Y DECODER Z CONTROL LINES ALU ...

  • Page 5

    ... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16A is a powerful microcontroller that provides a highly-flexible and cost- effective solution to many embedded control applications. The ATmega16A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

  • Page 6

    ... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16A as listed on 57. 2.2.5 Port C (PC7:PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

  • Page 7

    ... Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documen- tation for more details. 8154B–AVR–07/09 , even if the ADC is not used. If the ADC is used, it should be connected ATmega16A Table 27-2 on page CC 7 ...

  • Page 8

    ... Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. ATmega16A 8 Block Diagram of the AVR MCU Architecture ...

  • Page 9

    ... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8154B–AVR–07/09 ATmega16A 9 ...

  • Page 10

    ... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega16A ...

  • Page 11

    ... General R14 Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega16A 0 Addr. $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register Low Byte $1B X-register High Byte $1C Y-register Low Byte ...

  • Page 12

    ... Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 6.5.1 SPH and SPL – Stack Pointer High and Low Register Bit ATmega16A 12 The X-, Y-, and Z-registers ...

  • Page 13

    ... Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation clk CPU Total Execution Time Result Write Back ATmega16A SP4 SP3 SP2 SP1 R/W ...

  • Page 14

    ... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. ATmega16A 14 for details. “Boot Loader Support – Read-While-Write Self- 250. “ ...

  • Page 15

    ... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8154B–AVR–07/09 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set global interrupt enable ATmega16A 15 ...

  • Page 16

    ... Overview This section describes the different memories in the ATmega16A. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16A features an EEPROM Memory for data storage. All three memory spaces are linear and regular ...

  • Page 17

    ... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega16A are all accessible through all these addressing modes. The Register File is described in Figure 7-2. ...

  • Page 18

    ... EEPROM Data Memory The ATmega16A contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

  • Page 19

    ... I/O Memory The I/O space definition of the ATmega16A is shown in All ATmega16A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

  • Page 20

    ... Bits 15:9 – Res: Reserved Bits These bits are reserved bits in the ATmega16A and will always read as zero. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...

  • Page 21

    ... The examples 8154B–AVR–07/09 EEPROM Programming Time Number of Calibrated RC Oscillator Symbol 1. Uses 1 MHz clock, independent of CKSEL Fuse setting. ATmega16A for details about boot Table 7-1 lists the typical pro- (1) Cycles ...

  • Page 22

    ... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega16A 22 ; 8154B–AVR–07/09 ...

  • Page 23

    ... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; ATmega16A 23 ...

  • Page 24

    ... I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro- nously when clk ATmega16A 24 presents the principal clock systems in the AVR and their distribution. All of the clocks 32 ...

  • Page 25

    ... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 305. Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( ATmega16A (1) CKSEL3:0 1111 - 1010 1000 - 0101 0100 - 0001 = 3.0V) Number of Cycles CC 4 (4,096) ...

  • Page 26

    ... Figure 8-2. The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 8-3. CKOPT Note: ATmega16A 26 Crystal Oscillator Connections C2 C1 Crystal Oscillator Operating Modes Frequency Range CKSEL3:1 (MHz) (1) 101 ...

  • Page 27

    ... They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. Figure 8-2. By programming the CKOPT Fuse, the user can enable internal ATmega16A Additional Delay from Reset ( ...

  • Page 28

    ... The operating mode is selected by the fuses CKSEL3:0 as shown in Table 8-6. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-7. ATmega16A 28 Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Additional Delay Power-down and ...

  • Page 29

    ... The device is shipped with this option selected. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power-down and Power-save The device is shipped with this option selected. ATmega16A = 5.0V) Recommended Usage CC – BOD enabled 4.1 ms Fast rising power 65 ms Slowly rising power 4 ...

  • Page 30

    ... For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is opti- mized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. Note: ATmega16A 30 External Clock Drive Configuration EXTERNAL CLOCK ...

  • Page 31

    ... CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value Internal RC Oscillator Frequency Range. Min Frequency in Percentage of Nominal Frequency (%) $00 50 $7F 75 $FF 100 ATmega16A CAL4 CAL3 CAL2 CAL1 R/W R/W R/W R/W Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 0 CAL0 ...

  • Page 32

    ... SRAM are unaltered when the device wakes up from sleep Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. ATmega16A 32 presents the different clock systems in the ATmega16A, and their distri- Active Clock Domains and Wake Up Sources in the Different Sleep Modes Active Clock domains X ...

  • Page 33

    ... The device can wake up from either Timer Overflow or Output Compare 8154B–AVR–07/09 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page ATmega16A , and clk , while allowing the CPU FLASH “External Interrupts” on page 67 25. 33 ...

  • Page 34

    ... Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to configure the Brown-out Detector. ATmega16A 34 , allowing operation only of asynchronous ASY “Analog to Digital Converter” on page 207 “ ...

  • Page 35

    ... Timer” on page 41 for details on how to configure the Watchdog Timer. ) and the ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 53 /2, the input buffer will use excessive power. CC ATmega16A “Internal Volt- ) are stopped, the input buffers of the ADC for 35 ...

  • Page 36

    ... The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. ATmega16A ...

  • Page 37

    ... Reset Sources The ATmega16A has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...

  • Page 38

    ... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC Figure 10-2. MCU Start-up, RESET Tied to V ATmega16A 38 Power-on Reset Circuit Brown-out BODEN ...

  • Page 39

    ... Figure 10-4. External Reset During Operation 10.1.4 Brown-out Detection ATmega16A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...

  • Page 40

    ... Figure 10-6. Watchdog Reset During Operation 10.2 Internal Voltage Reference ATmega16A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V ref- erence to the ADC is generated from the internal bandgap reference. ...

  • Page 41

    ... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega16A resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol- lowed when the Watchdog is disabled ...

  • Page 42

    ... Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATmega16A and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

  • Page 43

    ... WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega16A Typical Time-out Typical Time-out 3. 5. 17 ...

  • Page 44

    ... Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega16A. For a general explanation of the AVR interrupt handling, refer to page 14. 11.2 Interrupt Vectors Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...

  • Page 45

    ... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16A is: Address Labels $000 $002 $004 $006 ...

  • Page 46

    ... GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels .org $1C00 $1C00 $1C02 $1C04 :. $1C28 ; $1C2A $1C2B ATmega16A 46 Code RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei < ...

  • Page 47

    ... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-Programming” on page 250 ATmega16A ; Enable interrupts 4 3 ...

  • Page 48

    ... GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret C Code Example void Move_interrupts(void Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); } ATmega16A 48 8154B–AVR–07/09 ...

  • Page 49

    ... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 54. Refer to the individual module sections for a full description of the alter- ATmega16A Figure 12-1. Refer to “Electrical Char Logic See Figure 23 "General Digital I/O" for Details 65. “ ...

  • Page 50

    ... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running. ATmega16A 50 (1) Pxn ...

  • Page 51

    ... Input 1 1 Input 0 X Output 1 X Output Figure 12-2, the PINxn Register bit and the preceding latch con- pd,max ATmega16A Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 12-3 ...

  • Page 52

    ... Figure 12-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK INSTRUCTIONS SYNC LATCH The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin ATmega16A 52 XXX PINxn r17 and t ...

  • Page 53

    ... Figure 12-2, the digital input signal can be clamped to ground at the input of the /2. CC ATmega16A “Alternate Port Functions” on page 54. 53 ...

  • Page 54

    ... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 12-5. Alternate Port Functions Note: ATmega16A 54 or GND is not recommended, since this may cause excessive currents if the pin is CC ...

  • Page 55

    ... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog Input/ output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. ATmega16A Fig- Table 12-3. If some 55 ...

  • Page 56

    ... PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16A 56 Port A Pins Alternate Functions Alternate Function ADC7 (ADC input channel 7) ADC6 (ADC input channel 6) ADC5 (ADC input channel 5) ADC4 (ADC input channel 4) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ...

  • Page 57

    ... SS (SPI Slave Select Input) AIN1 (Analog Comparator Negative Input) PB3 OC0 (Timer/Counter0 Output Compare Match Output) AIN0 (Analog Comparator Positive Input) PB2 INT2 (External Interrupt 2 Input) PB1 T1 (Timer/Counter1 External Counter Input) T0 (Timer/Counter0 External Counter Input) PB0 XCK (USART External Clock Input/Output) ATmega16A PA1/ADC1 ...

  • Page 58

    ... The XCK pin is active only when the USART oper- ates in Synchronous mode. Table 12-7 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATmega16A 58 and Table 12-8 relate the alternate functions of Port B to the overriding signals Figure 12-5 on page 54 ...

  • Page 59

    ... OC0 ENABLE 0 OC0 0 0 INT2 ENABLE 0 1 – INT2 INPUT AIN1 INPUT AIN0 INPUT ATmega16A PB5/MOSI PB4/SS SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR 0 SPI MSTR OUTPUT ...

  • Page 60

    ... When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK – Port C, Bit 2 TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. ATmega16A 60 Port C Pins Alternate Functions Alternate Function ...

  • Page 61

    ... Port C to the overriding signals Figure 12-5 on page 54. PC7/TOSC2 PC6/TOSC1 AS2 AS2 0 0 AS2 AS2 AS2 AS2 0 0 – – T/C2 OSC OUTPUT T/C2 OSC INPUT ATmega16A PC5/TDI PC4/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI – 61 ...

  • Page 62

    ... The OC2 pin is also the output pin for the PWM mode timer function. • ICP1 – Port D, Bit 6 ICP1 – Input Capture Pin: The PD6 pin can act as an Input Capture pin for Timer/Counter1. • OC1A – Port D, Bit 5 ATmega16A 62 PC3/TMS PC2/TCK JTAGEN ...

  • Page 63

    ... Table 12-14 relate the alternate functions of Port D to the overriding signals Figure 12-5 on page 54. PD7/OC2 PD6/ICP1 OC2 ENABLE 0 OC2 – ICP1 INPUT – – ATmega16A PD5/OC1A PD4/OC1B OC1A ENABLE OC1B ENABLE OC1A OC1B – – – – 63 ...

  • Page 64

    ... Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16A 64 PD3/INT1 PD2/INT0 INT1 ENABLE INT0 ENABLE 1 1 INT1 INPUT INT0 INPUT – – PD1/TXD PD0/RXD TXEN RXEN 0 PORTD0 • PUD TXEN ...

  • Page 65

    ... PINA6 PINA5 PINA4 N/A N/A N/A N PORTB7 PORTB6 PORTB5 PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R ATmega16A ACME PUD PSR2 PSR10 R/W R/W R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 R/W R/W ...

  • Page 66

    ... Initial Value 12.4.11 PORTD – Port D Data Register Bit Read/Write Initial Value 12.4.12 DDRD – Port D Data Direction Register Bit Read/Write Initial Value 12.4.13 PIND – Port D Input Pins Address Bit Read/Write Initial Value ATmega16A PINB7 PINB6 PINB5 PINB4 N/A N/A ...

  • Page 67

    ... If the level is sampled twice by the Watchdog Oscillator clock but SM2 SE SM1 SM0 R/W R/W R/W R Table 13-1. The value on the INT1 pin is sampled before ATmega16A 293. The MCU will “System Clock and ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R MCUCR ...

  • Page 68

    ... Therefore recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Reg- ister before the interrupt is re-enabled. ATmega16A 68 Interrupt 1 Sense Control ISC10 ...

  • Page 69

    ... Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. 8154B–AVR–07/ INT1 INT0 INT2 – R/W R/W R INTF1 INTF0 INTF2 – R/W R/W R ATmega16A – – IVSEL IVCE GICR R R R/W R – – – – GIFR ...

  • Page 70

    ... Note that when entering some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See Modes” on page 53 ATmega16A 70 for more information. “Digital Input Enable and Sleep ...

  • Page 71

    ... The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register 8154B–AVR–07/09 “Pinout ATmega16A” on page 2. CPU accessible I/O Registers, including I/O 82. TCCRn ...

  • Page 72

    ... The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram ATmega16A 72 for details. The compare match event will also set the Compare Flag (OCF0) Table 14-1 are also used extensively throughout the document ...

  • Page 73

    ... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 76. (See “Modes of Operation” on page shows a block diagram of the output compare unit. ATmega16A in the following. T0 76.). 73 ...

  • Page 74

    ... Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the output compare unit, inde- pendently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals ATmega16A 74 DATA BUS ...

  • Page 75

    ... The design of the output compare pin logic allows initialization of the OC0 state before the out- put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. 8154B–AVR–07/09 COMn1 Waveform COMn0 Generator FOCn clk I/O See “Register Description” on page 82. ATmega16A Figure 14-4 shows a simplified schematic OCn PORT D ...

  • Page 76

    ... This mode allows greater control of the compare match output frequency. It also sim- plifies the operation of counting external events. The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared. ATmega16A 76 Table 14-3 on page 83. For fast PWM mode, refer to Table 14-5 on page 75 ...

  • Page 77

    ... PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and 8154B–AVR–07/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- ATmega16A OCn Interrupt Flag Set (COMn1 OC0 clk_I ...

  • Page 78

    ... Phase Correct PWM Mode The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non- ATmega16A ...

  • Page 79

    ... OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The 8154B–AVR–07/ Table 14-5 on page ATmega16A Figure 14-7. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 84) ...

  • Page 80

    ... MAX value in all modes other than phase correct PWM mode. Figure 14-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 14-9 ATmega16A 80 f OCnPCPWM Figure 14-7 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn ...

  • Page 81

    ... I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ATmega16A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 81 ...

  • Page 82

    ... Waveform Generation to be used. Modes of operation sup- ported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Operation” on page ATmega16A 82 caler (f /8) clk_I/O ...

  • Page 83

    ... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See more details. shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase cor- ATmega16A (1) Update of TOV0 Flag ...

  • Page 84

    ... Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0 Register. ATmega16A 84 Compare Output Mode, Phase Correct PWM Mode ...

  • Page 85

    ... OCR0[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R ATmega16A R/W R/W R/W R OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R OCR0 TIMSK ...

  • Page 86

    ... The edge detector generates one clk (CSn2 edge it detects. Figure 15-1. T1/T0 Pin Sampling Tn clk I/O ATmega16A 86 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk ...

  • Page 87

    ... Since the edge detector uses ExtClk clk_I/O I/O Clear Synchronization Synchronization clk 1. The synchronization logic on the input pins ( ADTS2 ADTS1 ADTS0 R/W R/W R ATmega16A (1) T1 T1/T0) is shown in Figure – ACME PUD PSR2 R R/W R/W R /2.5. ...

  • Page 88

    ... A simplified block diagram of the 16-bit Timer/Counter is shown in placement of I/O pins, refer to bits and I/O pins, are shown in bold. The device specific I/O Register and bit locations are listed in the “Register Description” on page ATmega16A 88 Figure 1-1 on page 2. CPU accessible I/O Registers, including I/O 109. ...

  • Page 89

    ... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1-1 on page 2, Table 12-6 on page Timer/Counter1 pin placement and description. ATmega16A (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...

  • Page 90

    ... FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega16A 90 The compare match event will also set the Compare Match 204.) The Input Capture unit includes a digital filtering unit (Noise Definitions The counter reaches the BOTTOM when it becomes 0x0000 ...

  • Page 91

    ... Therefore, when both 8154B–AVR–07/09 ( Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H :. (1) unsigned int Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1 See “About Code Examples” on page 7. ATmega16A 91 ...

  • Page 92

    ... Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATmega16A 92 (1) (1) 1. See “About Code Examples” on page 7. ...

  • Page 93

    ... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; 1. See “About Code Examples” on page 7. “Timer/Counter0 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. ATmega16A 86. 93 ...

  • Page 94

    ... Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see The Timer/Counter Overflow (TOV1) Flag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. ATmega16A 94 DATA BUS (8-bit) ...

  • Page 95

    ... TOP value can be written to the ICR1 8154B–AVR–07/09 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ATmega16A Figure 16-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) ...

  • Page 96

    ... Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). ATmega16A 96 91. “Accessing 16-bit Registers” ...

  • Page 97

    ... DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = TOP Waveform Generator BOTTOM WGMn3:0 ATmega16A 99.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) (16-bit Comparator ) OCFnx (Int.Req.) COMnx1:0 OCnx 97 ...

  • Page 98

    ... COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the ATmega16A 98 91. ...

  • Page 99

    ... Waveform Generation mode (WGM13:0) and Compare Output 8154B–AVR–07/09 COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O See “Register Description” on page 109. Table 16-2 on page ATmega16A Q 1 OCnx OCnx Pin DDR Table 16-2, Table 16-3 and 110. For fast PWM mode refer to ...

  • Page 100

    ... It also simplifies the opera- tion of counting external events. The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATmega16A 100 98.) “Timer/Counter Timing Diagrams” on page Figure 16-6 ...

  • Page 101

    ... PWM mode well suited for power regulation, rectification, and DAC 8154B–AVR–07/ when OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega16A OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 1 101 ...

  • Page 102

    ... Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low ATmega16A 102 ( TOP ...

  • Page 103

    ... PWM modes, these modes are preferred for motor control applications. 8154B–AVR–07/09 Table 16-2 on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I/O 1 ATmega16A 110). The actual OC1x ) 103 ...

  • Page 104

    ... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an ATmega16A 104 ( ) ...

  • Page 105

    ... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 8154B–AVR–07/09 f OCnxPCPWM 16-9). ATmega16A Table 16-2 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP 110) ...

  • Page 106

    ... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 16-9 cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. ATmega16A 106 log R = ---------------------------------- - ...

  • Page 107

    ... OCRnx OCFnx Figure 16-11 8154B–AVR–07/09 f OCnxPFCPWM Figure 16-10 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ATmega16A f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value ...

  • Page 108

    ... The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 16-12. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) TOVn and ICFn (Update at TOP) Figure 16-13 ATmega16A 108 I/O Tn /8) I/O OCRnx - 1 shows the count sequence close to TOP in various modes. When using phase and ...

  • Page 109

    ... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value COM1A1 COM1A0 COM1B1 R/W R/W R ATmega16A /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 FOC1A FOC1B WGM11 R R BOTTOM + 1 TOP - 2 0 WGM10 TCCR1A ...

  • Page 110

    ... When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 16-2. COM1A1/COM1B1 Table 16-3 PWM mode. ATmega16A 110 Table 16-2 Compare Output Mode, non-PWM COM1A0/COM1B0 0 0 ...

  • Page 111

    ... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 103. ATmega16A (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OCnA/OCnB disconnected ...

  • Page 112

    ... Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the Noise Canceler is enabled. ATmega16A 112 Table 16-5. Modes of operation supported by the Timer/Counter (See “ ...

  • Page 113

    ... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge R/W R/W R/W R ATmega16A TCNT1[15:8] TCNT1[7:0] R/W R/W R Figure 0 TCNT1H TCNT1L R/W 0 113 ...

  • Page 114

    ... The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. ATmega16A 114 7 6 ...

  • Page 115

    ... TOV1 Flag, located in TIFR, is set OCF2 TOV2 ICF1 R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega16A OCIE1A OCIE1B TOIE1 OCIE0 R/W R/W R/W R ...

  • Page 116

    ... TOV1 Flag is set when the timer overflows. Refer to behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega16A 116 Table 16-5 on page 112 for the TOV1 Flag ...

  • Page 117

    ... Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. 8154B–AVR–07/09 “Pinout ATmega16A” on page 130. TCCRn count ...

  • Page 118

    ... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 17-2 shows a block diagram of the counter and its surrounding environment. ATmega16A 118 ). T2 for details. The compare match event will also set the Compare Flag (OCF2) Table 17-1 Definitions The counter reaches the BOTTOM when it becomes zero (0x00) ...

  • Page 119

    ... T2 is present or not. A CPU write overrides (has priority over) all counter clear or T2 122. can be used for generating a CPU interrupt. TOV2 122). Figure 17-3 shows a block diagram of the output compare unit. ATmega16A TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler (“Modes of Operation” ...

  • Page 120

    ... TCNT2 when using the output compare unit, inde- pendently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. ATmega16A 120 DATA BUS OCRn ...

  • Page 121

    ... COMn0 D Q Generator FOCn OCn D Q PORT D Q DDR clk I/O “Register Description” on page 130. Table 17-3 on page 131. For fast PWM mode, refer to Table 17-5 on page ATmega16A Figure 17-4 shows a simplified schematic 1 OCn Pin 0 Table 17-4 on page 132. 121 ...

  • Page 122

    ... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. ATmega16A 122 121.). “Timer/Counter Timing Diagrams” on page Flag in this case behaves like a ninth TOV2 Flag, the timer resolution can be increased by software ...

  • Page 123

    ... PWM mode is shown in 8154B–AVR–07/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 Flag is set in the same timer clock cycle that the TOV2 Figure 17-6. The TCNT2 value is in the timing diagram shown as a his- ATmega16A OCn Interrupt Flag Set (COMn1 OC2 clk_I 123 ...

  • Page 124

    ... OC2 toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 17.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. ATmega16A 124 set each time the counter reaches MAX ...

  • Page 125

    ... PWM frequency for the output when using phase correct PWM can be calculated by the follow- ing equation: 8154B–AVR–07/09 TCNTn OCn OCn Period 1 TOV2 f OCnPCPWM ATmega16A OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 set each time the counter reaches BOTTOM. The Table 17-5 on page f ...

  • Page 126

    ... MAX value in all modes other than phase correct PWM mode. Figure 17-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 17-9 ATmega16A 126 Figure 17-7 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled ...

  • Page 127

    ... I/O Tn /8) I/O MAX - 1 shows the setting of OCF2 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ATmega16A /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 127 ...

  • Page 128

    ... OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. ATmega16A 128 caler (f /8) ...

  • Page 129

    ... Interrupt Flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. 8154B–AVR–07/09 ) again becomes active, TCNT2 will read as the previous value (before entering I/O ATmega16A 129 ...

  • Page 130

    ... The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. ATmega16A 130 clk ...

  • Page 131

    ... Compare Output Mode, non-PWM Mode COM20 Description 0 0 Normal port operation, OC2 disconnected Toggle OC2 on compare match 1 0 Clear OC2 on compare match 1 1 Set OC2 on compare match ATmega16A Table 17-2 and “Modes of Operation” (1) Update of TOV2 Flag TOP OCR2 Set on 0xFF Immediate MAX 0xFF TOP ...

  • Page 132

    ... The three Clock Select bits select the clock source to be used by the Timer/Counter, see 17-6. Table 17-6. CS22 ATmega16A 132 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM Compare Output Mode, Fast PWM Mode COM20 Description 0 Normal port operation, OC2 disconnected. 1 Reserved 0 Clear OC2 on compare match, set OC2 at BOTTOM, ...

  • Page 133

    ... TCNT2[7:0] R/W R/W R/W R OCR2[7:0] R/W R/W R/W R – – – – AS2 R ATmega16A R/W R/W R/W R R/W R/W R/W R TCN2UB OCR2UB TCR2UB When AS2 is I/O TCNT2 OCR2 ASSR 133 ...

  • Page 134

    ... Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. 17.11.7 SFIOR – Special Function IO Register Bit Read/Write Initial Value • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 ATmega16A 134 OCIE2 TOIE2 ...

  • Page 135

    ... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. 8154B–AVR–07/09 ATmega16A 135 ...

  • Page 136

    ... Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16A and peripheral devices or between several AVR devices. The ATmega16A SPI iSPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two Shift Registers, and a Master clock generator ...

  • Page 137

    ... Port Functions” on page 8154B–AVR–07/09 MSB MASTER LSB MISO 8 BIT SHIFT REGISTER MOSI SPI SCK CLOCK GENERATOR SS Table 18-1 on page 138. For more details on automatic port overrides, refer to 54. ATmega16A MSB SLAVE LSB MISO 8 BIT SHIFT REGISTER MOSI SHIFT SCK ENABLE SS 137 ...

  • Page 138

    ... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega16A 138 SPI Pin Overrides Direction, Master SPI ...

  • Page 139

    ... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 7. ATmega16A 139 ...

  • Page 140

    ... Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return data register */ return SPDR; } Note: ATmega16A 140 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See “About Code Examples” on page 7. 8154B–AVR–07/09 ...

  • Page 141

    ... Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 18-4, as done below: CPOL and CPHA Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) ATmega16A Figure Trailing Edge SPI Mode Setup (Falling) 0 Sample (Falling) 1 Setup (Rising) 2 ...

  • Page 142

    ... Figure 18-2. SPI Transfer Format with CPHA = 0 Figure 18-3. SPI Transfer Format with CPHA = 1 ATmega16A 142 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 LSB first (DORD = 1) LSB Bit 1 ...

  • Page 143

    ... Figure 18-2 and Figure 18-3 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 18-2 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega16A CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 18-3 for an example ...

  • Page 144

    ... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega16A is also used for program memory and EEPROM down- loading or uploading. See ATmega16A 144 ...

  • Page 145

    ... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8154B–AVR–07/ MSB R/W R/W R/W R ATmega16A LSB R/W R/W R/W R SPDR Undefined 145 ...

  • Page 146

    ... Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. A simplified block diagram of the USART transmitter is shown in ATmega16A 146 Figure 19-1. CPU accessible I/O Registers and I/O pins are shown in bold. 8154B–AVR–07/09 ...

  • Page 147

    ... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1-1 on page 2, Table 12-14 on page pin placement. ATmega16A Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL Receiver ...

  • Page 148

    ... Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 19-2 ATmega16A 148 shows a block diagram of the clock generation logic. Figure 19-1) if the Buffer Registers 8154B– ...

  • Page 149

    ... Input from XCK pin (Internal Signal). Used for synchronous Slave Clock output to XCK pin (Internal Signal). Used for synchronous Master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculat- ATmega16A U2X / ...

  • Page 150

    ... The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. ATmega16A 150 Equations for Calculating Baud Rate Register Setting BAUD 1 ...

  • Page 151

    ... Bits inside brackets are (IDLE Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). An IDLE line must high. ATmega16A Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 151 ...

  • Page 152

    ... The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 regis- ters. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC. ATmega16A 152 ⊕ … ...

  • Page 153

    ... Set baud rate */ UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); 1. See “About Code Examples” on page 7. ATmega16A 153 ...

  • Page 154

    ... If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16. ATmega16A 154 (1) UDR,r16 (1) ...

  • Page 155

    ... UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRB is static. (i.e., only the TXB8 bit of the UCSRB Register is used after initialization). ATmega16A 155 ...

  • Page 156

    ... Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant ATmega16A 156 8154B–AVR–07/09 ...

  • Page 157

    ... UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret (1) /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “About Code Examples” on page 7. ATmega16A 157 ...

  • Page 158

    ... Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega16A 158 (1) r18, UCSRA ...

  • Page 159

    ... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error. 8154B–AVR–07/09 and “Parity Checker” on page 159. ATmega16A 159 ...

  • Page 160

    ... Note the larger time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). ATmega16A 160 (1) r16, UDR (1) 1. See “ ...

  • Page 161

    ... Note that the receiver only uses the first stop bit of a frame. Figure 19-7 of the next frame. 8154B–AVR–07/09 IDLE Figure 19 shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega16A START shows the sampling of the data bits and the par- BIT ...

  • Page 162

    ... Table 19-2) base frequency, the receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow ATmega16A 162 Figure 19-7 ...

  • Page 163

    ... ATmega16A Max Total Error Recommended Max Receiver (%) Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.5 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± ...

  • Page 164

    ... When doing a write access of this I/O location, the high bit of the value written, the USART Reg- ister Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC setting will be updated. ATmega16A 164 8154B–AVR–07/09 ...

  • Page 165

    ... UCSRC,r16 :. ( Set UBRRH UBRRH = 0x02 Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1 See “About Code Examples” on page 7. (1) ATmega16A 165 ...

  • Page 166

    ... Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. ATmega16A 166 (1) 1. See “About Code Examples” on page 7. ...

  • Page 167

    ... This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effectively dou- bling the transfer rate for asynchronous communication. 8154B–AVR–07/ RXC TXC UDRE ATmega16A DOR PE U2X MPCM R R R/W R UCSRA 167 ...

  • Page 168

    ... Size frame the receiver and transmitter use. • Bit 1 – RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. ATmega16A 168 “Multi-processor Communication Mode” on page 7 ...

  • Page 169

    ... UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation UPM Bits Settings UPM1 UPM0 USBS Bit Settings USBS 0 1 ATmega16A UPM0 USBS UCSZ1 UCSZ0 R/W R/W R/W R section which describes how to access this register. Parity Mode Disabled Reserved Enabled, Even Parity ...

  • Page 170

    ... UBRRH. The URSEL must be zero when writing the UBRRH. • Bit 14:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. ATmega16A 170 UCSZ Bits Settings UCSZ1 ...

  • Page 171

    ... ATmega16A Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0. ...

  • Page 172

    ... Max 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% ATmega16A 172 f = 4.0000 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0. ...

  • Page 173

    ... Mbps 691.2 kbps ATmega16A MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0. ...

  • Page 174

    ... Table 19-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max 1. ATmega16A 174 U2X = 0 UBRR 416 207 103 Mbps UBRR = 0, Error = 0. 16.0000 MHz osc ...

  • Page 175

    ... TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 20-1. TWI Bus Interconnection SDA SCL 8154B–AVR–07/09 Device 1 Device 2 Device 3 ATmega16A V CC ........ Device 175 ...

  • Page 176

    ... Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other Master should try to seize control of the bus. A special case occurs when a new START ATmega16A 176 TWI Terminology Description The device that initiates and terminates a transmission ...

  • Page 177

    ... Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several Slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. 8154B–AVR–07/09 START STOP START ATmega16A REPEATED START STOP 177 ...

  • Page 178

    ... SCL low period will not affect the SCL high period, which is determined by the Master consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 20-6 between the SLA+R/W and the STOP condition, depending on the software protocol imple- mented by the application software. ATmega16A 178 Addr MSB 1 2 START ...

  • Page 179

    ... Addr MSB Addr LSB R/W ACK START SLA+R/W TA low SCL from Master A SCL from Master B SCL bus Line TB Masters Start Counting Low Period ATmega16A Data MSB Data LSB Data Byte TA high TB low high Masters Start Counting High Period ACK 9 STOP 179 ...

  • Page 180

    ... This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATmega16A 180 START SDA from ...

  • Page 181

    ... Control Address/Data Shift Arbitration detection Ack Register (TWDR) Address Match Unit Address Register Status Register (TWAR) (TWSR) Address Comparator ATmega16A Figure 20-9. All registers Bit Rate Generator Prescaler Bit Rate Register (TWBR) Control Unit Control Register (TWCR) TWI Unit State Machine and ...

  • Page 182

    ... TWI transmission to continue. The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition • After the TWI has transmitted SLA+R/W ATmega16A 182 SCL frequency Note: Pull-up resistor values should be selected according to the SCL frequency and the capaci- tive bus line load ...

  • Page 183

    ... TWCR, making sure that TWINT is written to one SLA+W A Data 4. TWINT set. Status code indicates SLA+W sent, ACK received ATmega16A 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one A STOP Indicates 6 ...

  • Page 184

    ... Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: • When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL line is pulled low until TWINT is cleared. ATmega16A 184 8154B–AVR–07/09 ...

  • Page 185

    ... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega16A Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits ...

  • Page 186

    ... The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is trans- mitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. ATmega16A 186 to Figure 20-18, circles are used to indicate that the TWINT Flag is set ...

  • Page 187

    ... RECEIVER TWINT TWEA TWSTA TWINT TWEA TWSTA Table 20-2. TWINT TWEA TWSTA TWINT TWEA TWSTA TWINT TWEA TWSTA ATmega16A V CC ........ Device n R1 TWSTO TWWC TWEN Table 20-2). In order to enter MT mode, TWSTO TWWC TWEN TWSTO TWWC TWEN TWSTO TWWC TWEN TWSTO TWWC ...

  • Page 188

    ... NOT ACK has been received $28 Data byte has been transmitted; ACK has been received $30 Data byte has been transmitted; NOT ACK has been received $38 Arbitration lost in SLA+W or data bytes ATmega16A 188 Application Software Response To TWCR To/from TWDR STO TWINT STA 0 1 Load SLA+W ...

  • Page 189

    ... MT S SLA W A $08 $ $38 A $68 $78 DATA From master to slave From slave to master 20-13). In order to enter a Master mode, a START condition must be transmitted. ATmega16A DATA A P $28 R SLA S $ $30 Other master Other master continues continues $38 Other master ...

  • Page 190

    ... After a repeated START condition (state $10) the Two-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. ATmega16A 190 Device 1 Device 2 ...

  • Page 191

    ... Read data byte Read data byte Read data byte 1 ATmega16A TWEA Next Action Taken by TWI Hardware X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to masTer Transmitter mode ...

  • Page 192

    ... In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure are zero or are masked to zero. Figure 20-15. Data Transfer in Slave Receiver Mode SDA SCL To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR Value ATmega16A 192 MR S SLA R A DATA $08 $40 ...

  • Page 193

    ... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 8154B–AVR–07/09 TWINT TWEA TWSTA TWSTO ATmega16A TWWC TWEN – TWIE Table 20-4. 193 ...

  • Page 194

    ... Previously addressed with general call; data has been received; NOT ACK has been returned $A0 A STOP condition or repeated START condition has been received while still addressed as Slave ATmega16A 194 Application Software Response To TWCR To/from TWDR STO TWINT STA TWDR action or ...

  • Page 195

    ... Arbitration lost as master and addressed as slave by general call DATA From master to slave From slave to master 20-17). All the status codes mentioned in this section assume that the prescaler bits Device 1 Device 2 SLAVE MASTER TRANSMITTER RECEIVER ATmega16A A DATA A DATA $60 $80 $80 $88 A $68 A DATA ...

  • Page 196

    ... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. ATmega16A 196 TWA6 TWA5 ...

  • Page 197

    ... No TWDR action TWDR action TWDR action 1 ATmega16A TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should ...

  • Page 198

    ... In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2. The EEPROM must be instructed what location should be read 3. The reading must be performed ATmega16A 198 S SLA R A ...

  • Page 199

    ... SDA while another Master outputs a zero will lose the arbitration. 8154B–AVR–07/09 Master Transmitter SLA+W A ADDRESS REPEATED START Transmitted from Master to Slave Device 1 Device 2 Device 3 MASTER SLAVE MASTER TRANSMITTER RECEIVER TRANSMITTER ATmega16A Master Receiver Rs SLA+R A DATA Transmitted from Slave to Master V CC ........ Device STOP R2 199 ...

  • Page 200

    ... The TWCR is used to control the operation of the TWI used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the ATmega16A 200 Figure 20-21. Possible status values are given in circles. ...