MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Table 13-1.
ISC11
0
0
1
1
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-2.
ISC01
0
0
1
1
13.1.2
MCUCSR – MCU Control and Status Register
Bit
Read/Write
Initial Value
• Bit 6 – ISC2: Interrupt Sense Control 2
The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and
the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on
INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the inter-
rupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum
pulse width given in
Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an
interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt
Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt
Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Reg-
ister before the interrupt is re-enabled.
ATmega16A
68
Interrupt 1 Sense Control
ISC10
Description
0
The low level of INT1 generates an interrupt request.
1
Any logical change on INT1 generates an interrupt request.
0
The falling edge of INT1 generates an interrupt request.
1
The rising edge of INT1 generates an interrupt request.
Table
13-2. The value on the INT0 pin is sampled before detecting
Interrupt 0 Sense Control
ISC00
Description
0
The low level of INT0 generates an interrupt request.
1
Any logical change on INT0 generates an interrupt request.
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
7
6
5
4
JTD
ISC2
JTRF
R/W
R/W
R
R/W
0
0
0
“External Interrupts Characteristics” on page 297
3
2
1
0
WDRF
BORF
EXTRF
PORF
R/W
R/W
R/W
R/W
See Bit Description
will generate an interrupt.
8154B–AVR–07/09
MCUCSR