ATMEGA16A-PU | |
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Manufacturer Part Number | ATMEGA16A-PU |
Description | MCU AVR 16K FLASH 16MHZ 40-PDIP |
Manufacturer | Atmel |
Series | AVR® ATmega |
ATMEGA16A-PU datasheets |
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Specifications of ATMEGA16A-PU | |||
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Core Processor | AVR | Core Size | 8-Bit |
Speed | 16MHz | Connectivity | I²C, SPI, UART/USART |
Peripherals | Brown-out Detect/Reset, POR, PWM, WDT | Number Of I /o | 32 |
Program Memory Size | 16KB (8K x 16) | Program Memory Type | FLASH |
Eeprom Size | 512 x 8 | Ram Size | 1K x 8 |
Voltage - Supply (vcc/vdd) | 2.7 V ~ 5.5 V | Data Converters | A/D 8x10b |
Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
Package / Case | 40-DIP (0.600", 15.24mm) | Processor Series | ATMEGA16x |
Core | AVR8 | Data Bus Width | 8 bit |
Data Ram Size | 1 KB | Interface Type | 2-Wire/SPI/USART |
Maximum Clock Frequency | 16 MHz | Number Of Programmable I/os | 32 |
Number Of Timers | 3 | Maximum Operating Temperature | + 85 C |
Mounting Style | Through Hole | 3rd Party Development Tools | EWAVR, EWAVR-BL |
Development Tools By Supplier | ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT | Minimum Operating Temperature | - 40 C |
On-chip Adc | 8-ch x 10-bit | Package | 40PDIP |
Device Core | AVR | Family Name | ATmega |
Maximum Speed | 16 MHz | Operating Supply Voltage | 3.3|5 V |
Controller Family/series | AVR MEGA | No. Of I/o's | 32 |
Eeprom Memory Size | 512Byte | Ram Memory Size | 1KB |
Cpu Speed | 16MHz | Rohs Compliant | Yes |
For Use With | ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-
tive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clk
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC2).
Unit” on page 119.
which can be used to generate an output compare interrupt request.
17.2.2
Definitions
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2
counter value and so on). The definitions in
document.
Table 17-1.
BOTTOM
MAX
TOP
17.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
– Asynchronous Status Register” on page
“Timer/Counter Prescaler” on page
17.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
17-2
shows a block diagram of the counter and its surrounding environment.
ATmega16A
118
).
T2
for details. The compare match event will also set the Compare Flag (OCF2)
Table 17-1
Definitions
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2 Register. The assignment is dependent
on the mode of operation.
is by default equal to the MCU clock, clk
T2
133. For details on clock sources and prescaler, see
130.
See “Output Compare
are also used extensively throughout the
. When the AS2
I/O
“ASSR
Figure
8154B–AVR–07/09
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