MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 200/352

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Losing Masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
• Two or more Masters are accessing different Slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in
Figure 20-21. Possible Status Codes Caused by Arbitration
START
20.9
Register Description
20.9.1
TWBR – TWI Bit Rate Register
Bit
Read/Write
Initial Value
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 181
20.9.2
TWCR – TWI Control Register
Bit
Read/Write
Initial Value
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
ATmega16A
200
Figure
20-21. Possible status values are given in circles.
SLA
Arbitration lost in SLA
Own
No
38
Address / General Call
received
Yes
Write
68/78
Direction
Read
7
6
5
4
TWBR7
TWBR6
TWBR5
TWBR4
R/W
R/W
R/W
R/W
0
0
0
0
for calculating bit rates.
7
6
5
4
TWINT
TWEA
TWSTA
TWSTO
R/W
R/W
R/W
R/W
0
0
0
0
Data
Arbitration lost in Data
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
B0
Data byte will be transmitted and ACK should be received
3
2
1
0
TWBR3
TWBR2
TWBR1
TWBR0
R/W
R/W
R/W
R/W
0
0
0
0
“Bit Rate Generator
3
2
1
0
TWWC
TWEN
TWIE
R
R/W
R
R/W
0
0
0
0
8154B–AVR–07/09
STOP
TWBR
TWCR