MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Figure 19-1. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The clock generation logic consists of synchronization logic for external clock input used by syn-
chronous Slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, parity generator and control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the receiver includes a parity checker, control logic, a Shift Register and a two level
receive buffer (UDR). The receiver supports the same frame formats as the transmitter, and can
detect frame error, data overrun and parity errors.
8154B–AVR–07/09
(1)
UBRR[H:L]
BAUD RATE GENERATOR
UDR (Transmit)
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
UDR (Receive)
UCSRA
1. Refer to
Figure 1-1 on page
2,
Table 12-14 on page
pin placement.
ATmega16A
Clock Generator
OSC
SYNC LOGIC
PIN
CONTROL
Transmitter
TX
CONTROL
PARITY
GENERATOR
PIN
CONTROL
Receiver
CLOCK
RX
RECOVERY
CONTROL
DATA
PIN
RECOVERY
CONTROL
PARITY
CHECKER
UCSRB
UCSRC
64, and
Table 12-8 on page 59
XCK
TxD
RxD
for USART
147