ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 147

• Manufacturer Part Number: ATMEGA16A-PU
• Description: MCU AVR 16K FLASH 16MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8154B–AVR–07/09
Figure 19-1. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The clock generation logic consists of synchronization logic for external clock input used by syn-
chronous Slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, parity generator and control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the receiver includes a parity checker, control logic, a Shift Register and a two level
receive buffer (UDR). The receiver supports the same frame formats as the transmitter, and can
detect frame error, data overrun and parity errors.
1. Refer to
pin placement.
Figure 1-1 on page
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
UDR (Receive)
UBRR[H:L]
2,
(1)
Table 12-14 on page
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
64, and
Table 12-8 on page 59
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
ATmega16A
Receiver
UCSRC
XCK
RxD
TxD
for USART
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