ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 349

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
10 000
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
9 800
23 JTAG Interface and On-chip Debug System ...................................... 226
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 232
25 Boot Loader Support – Read-While-Write Self-Programming ......... 250
8154B–AVR–07/09
22.5
22.6
22.7
22.8
22.9
22.10
22.11
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
23.10
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
25.1
25.2
25.3
25.4
25.5
25.6
25.7
Prescaling and Conversion Timing ................................................................210
Changing Channel or Reference Selection ...................................................213
ADC Noise Canceler .....................................................................................215
ADC Conversion Result .................................................................................219
Register Description ......................................................................................221
ADLAR = 0 .....................................................................................................224
ADLAR = 1 .....................................................................................................224
Features ........................................................................................................226
Overview ........................................................................................................226
TAP – Test Access Port ................................................................................226
TAP Controller ...............................................................................................228
Using the Boundary-scan Chain ....................................................................229
Using the On-chip Debug System .................................................................229
On-chip Debug Specific JTAG Instructions ...................................................230
Using the JTAG Programming Capabilities ...................................................231
Register Description ......................................................................................231
Bibliography ...................................................................................................231
Features ........................................................................................................232
Overview ........................................................................................................232
Data Registers ...............................................................................................232
Boundary-scan Specific JTAG Instructions ...................................................234
Boundary-scan Chain ....................................................................................235
Boundary-scan Order ....................................................................................245
Boundary-scan Description Language Files ..................................................249
Register Description ......................................................................................249
Features ........................................................................................................250
Overview ........................................................................................................250
Application and Boot Loader Flash Sections .................................................250
Read-While-Write and no Read-While-Write Flash Sections ........................251
Boot Loader Lock Bits ...................................................................................253
Entering the Boot Loader Program ................................................................254
Addressing the Flash during Self-Programming ............................................256
ATmega16A
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