ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 21
Manufacturer Part Number
MCU AVR 16K FLASH 16MHZ 40-PDIP
1.ATMEGA16A-MU.pdf (352 pages)
2.ATMEGA16A-MU.pdf (19 pages)
Specifications of ATMEGA16A-PU
I²C, SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
16KB (8K x 16)
Program Memory Type
512 x 8
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
8-ch x 10-bit
Operating Supply Voltage
No. Of I/o's
Eeprom Memory Size
Ram Memory Size
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See
Support – Read-While-Write Self-Programming” on page 250
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM Access, the EEAR or EEDR reGister will be modified, causing the
interrupted EEPROM Access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to a logic one to
trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested
data is available immediately. When the EEPROM is read, the CPU is halted for four cycles
before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses.
gramming time for EEPROM access from the CPU.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (for example by disabling inter-
rupts globally) so that no interrupts will occur during execution of these functions. The examples
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
EEPROM write (from CPU)
1. Uses 1 MHz clock, independent of CKSEL Fuse setting.
EEPROM Programming Time
Number of Calibrated RC Oscillator
Typ Programming Time
for details about boot
lists the typical pro-