ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 302

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 27-6.
Notes:
27.10 Parallel Programming Characteristics
302
Symbol
R
R
V
REF
AIN
INT
1. Values are guidelines only.
2. Minimum for AVCC is 2.7V.
3. Maximum for AVCC is 5.5V.
ATmega16A
Parameter
Internal Voltage Reference
Reference Input Resistance
Analog Input Resistance
ADC Characteristics (Continued)
Figure 27-8. Parallel Programming Timing, Including some General Timing Requirements
Figure 27-9. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
(DATA, XA0/1, BS1, BS2)
PAGEL
XTAL1
DATA
BS1
XA0
XA1
1. The timing requirements shown in
ing operation.
Data & Contol
RDY/BSY
PAGEL
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
WR
Condition
t
t
BVPH
DVXH
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
Figure 27-8
t
t
t
t
t
XLXH
XLDX
PLBX
XLWL
PLWL
(i.e., t
t
(HIGH BYTE)
BVWL
LOAD DATA
Min
DATA (High Byte)
2.3
DVXH
(1)
t
t
WL WH
XLPH
WLRL
LOAD DATA
, t
XHXL
Typ
, and t
100
2.6
32
t
PLXH
(1)
t
WLBX
XLDX
LOAD ADDRESS
(LOW BYTE)
Max
) also apply to load-
ADDR1 (Low Byte)
2.9
8154B–AVR–07/09
(1)
t
WLRH
Units
(1)
V

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