ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 148

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
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10 000
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ATMEGA16A-PU
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ATMEL
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19.2.1
19.3
148
Clock Generation
ATmega16A
AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
The following control bits have changed name, but have same functionality and register location:
The clock generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asyn-
chronous, Master Synchronous and Slave Synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-
ation. Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using Synchronous mode.
Figure 19-2
• Bit locations inside all USART Registers
• Baud Rate Generation
• Transmitter Operation
• Transmit Buffer Functionality
• Receiver Operation
• A second Buffer Register has been added. The two Buffer Registers operate as a circular
• The receiver Shift Register can now act as a third buffer level. This is done by allowing the
• CHR9 is changed to UCSZ2
• OR is changed to DOR
FIFO buffer. Therefore the UDR must only be read once for each incoming data! More
important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) are
buffered with the data in the receive buffer. Therefore the status bits must always be read
before the UDR Register is read. Otherwise the error status will be lost since the buffer state
is lost.
received data to remain in the serial Shift Register (see
are full, until a new start bit is detected. The USART is therefore more resistant to Data
OverRun (DOR) error conditions.
shows a block diagram of the clock generation logic.
Figure
19-1) if the Buffer Registers
8154B–AVR–07/09

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