ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 65

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
10 000
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
9 800
Part Number:
ATMEGA16A-PU
Manufacturer:
Microchip Technology
Quantity:
1 002
12.4
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
8154B–AVR–07/09
Register Description
SFIOR – Special Function I/O Register
PORTA – Port A Data Register
DDRA – Port A Data Direction Register
PINA – Port A Input Pins Address
PORTB – Port B Data Register
DDRB – Port B Data Direction Register
• Bit 2 – PUD: Pull-up disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 50
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADTS2
PORTA7
PORTB7
PINA7
DDB7
DDA7
R/W
R/W
R/W
R/W
R/W
N/A
7
0
R
7
0
7
0
7
7
0
7
0
PORTA6
PORTB6
ADTS1
PINA6
DDB6
DDA6
R/W
R/W
R/W
R/W
R/W
N/A
R
6
0
6
0
6
6
0
6
0
6
0
for more details about this feature.
PORTA5
PORTB5
PINA5
DDB5
DDA5
ADTS0
R/W
R/W
R/W
R/W
N/A
R/W
5
0
R
5
0
5
0
5
5
0
5
0
PORTA4
PORTB4
PINA4
DDB4
DDA4
R/W
R/W
R/W
R/W
N/A
4
0
R
4
0
4
0
4
4
0
R
4
0
PORTA3
PORTB3
PINA3
DDB3
DDA3
R/W
R/W
R/W
R/W
N/A
3
0
R
3
0
ACME
3
0
3
3
0
R/W
3
0
PORTA2
PORTB2
PINA2
DDB2
DDA2
R/W
R/W
R/W
R/W
N/A
2
0
R
2
0
2
0
2
2
0
PUD
R/W
2
0
PORTA1
PORTB1
PINA1
DDB1
DDA1
R/W
R/W
R/W
R/W
N/A
PSR2
R/W
1
0
R
1
0
1
0
1
1
0
ATmega16A
1
0
PORTA0
PORTB0
PINA0
DDB0
PSR10
DDA0
R/W
R/W
R/W
R/W
N/A
R/W
0
0
R
0
0
0
0
0
0
0
0
0
PORTA
PORTB
DDRB
SFIOR
DDRA
PINA
“Con-
65

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