ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 224

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
10 000
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
9 800
Part Number:
ATMEGA16A-PU
Manufacturer:
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Quantity:
1 002
22.9.3
ADLAR = 0
ADLAR = 1
224
ATmega16A
ADCL and ADCH – The ADC Data Register
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
Table 22-5.
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
ADC7
ADC9
ADC1
15
15
R
R
R
R
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
ADPS1
6
0
0
6
0
0
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
5
0
0
5
0
0
ADC4
ADC6
12
12
R
R
R
R
4
0
0
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
3
0
0
3
0
0
ADC2
ADC4
10
10
R
R
R
R
2
0
0
2
0
0
ADC9
ADC1
ADC3
Division Factor
R
R
R
R
9
1
0
0
9
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
0
0
0
8154B–AVR–07/09
ADCH
ADCH
ADCL
ADCL

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