ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 68
Manufacturer Part Number
MCU AVR 16K FLASH 16MHZ 40-PDIP
Specifications of ATMEGA16A-PU
I²C, SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
16KB (8K x 16)
Program Memory Type
512 x 8
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
8-ch x 10-bit
Operating Supply Voltage
No. Of I/o's
Eeprom Memory Size
Ram Memory Size
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MCUCSR – MCU Control and Status Register
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
• Bit 6 – ISC2: Interrupt Sense Control 2
The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and
the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on
INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the inter-
rupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum
pulse width given in
Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an
interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt
Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt
Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Reg-
ister before the interrupt is re-enabled.
Interrupt 1 Sense Control
Interrupt 0 Sense Control
“External Interrupts Characteristics” on page 297
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
13-2. The value on the INT0 pin is sampled before detecting
See Bit Description
will generate an interrupt.