ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 111

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Manufacturer
Quantity
Price
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Part Number:
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8154B–AVR–07/09
Table 16-3.
Note:
Table 16-4
correct or the phase and frequency correct, PWM mode.
Table 16-4.
Note:
• Bit 3 – FOC1A: Force Output Compare for Channel A
• Bit 2 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at BOTTOM.
PWM Mode” on page 101.
“Phase Correct PWM Mode” on page 103.
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
Compare Output Mode, Fast PWM
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
(1)
COM1A0/COM1B0
COM1A0/COM1B0
0
1
0
1
0
1
0
1
for more details.
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 15: Toggle OC1A on Compare Match,
OC1B disconnected (normal port operation).
For all other WGM13:0 settings, normal port
operation, OCnA/OCnB disconnected.
Clear OC1A/OC1B on compare match, set
OC1A/OC1B at BOTTOM,
(non-inverting mode)
Set OC1A/OC1B on compare match, clear
OC1A/OC1B at BOTTOM,
(inverting mode)
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 9 or 14: Toggle OCnA on Compare
Match, OCnB disconnected (normal port
operation).
For all other WGM13:0 settings, normal port
operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on compare match when up-
counting. Set OC1A/OC1B on compare match
when downcounting.
Set OC1A/OC1B on compare match when up-
counting. Clear OC1A/OC1B on compare match
when downcounting.
(1)
for more details.
ATmega16A
See “Fast
See
111

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