ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 131

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8154B–AVR–07/09
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 3, 6 – WGM2[1:0]: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 17-2.
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set
in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
normal or CTC mode (non-PWM).
Table 17-3.
Mode
0
1
2
3
COM21
0
0
1
1
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
122.
WGM21
Table 17-3
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
Waveform Generation Mode Bit Description
Compare Output Mode, non-PWM Mode
COM20
WGM20
(PWM2)
shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
0
1
0
1
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Toggle OC2 on compare match
Clear OC2 on compare match
Set OC2 on compare match
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
Table 17-2
(1)
TOP
0xFF
0xFF
OCR2
0xFF
and
Update of
OCR2
Immediate
Immediate
BOTTOM
TOP
ATmega16A
“Modes of Operation”
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
131

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