ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 86

MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part Number
ATMEGA16A-PU
Description
MCU AVR 16K FLASH 16MHZ 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
10 000
Company:
Part Number:
ATMEGA16A-PU
Manufacturer:
ATMEL
Quantity:
9 800
Part Number:
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Manufacturer:
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15. Timer/Counter0 and Timer/Counter1 Prescalers
15.1
15.2
15.3
15.4
86
Overview
Internal Clock Source
Prescaler Reset
External Clock Source
ATmega16A
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters
can have different prescaler settings. The description below applies to both Timer/Counter1 and
Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the clock select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 15-1. T1/T0 Pin Sampling
CLK_I/O
T1
/clk
clk
Tn
/1024.
I/O
T0
). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
D
LE
CLK_I/O
Q
Synchronization
). Alternatively, one of four taps from the prescaler can be used as a
D
Q
T1
/clk
T
0
pulse for each positive (CSn2:0 = 7) or negative
D
CLK_I/O
Q
/8, f
Edge Detector
CLK_I/O
/64, f
clk
CLK_I/O
8154B–AVR–07/09
I/O
Tn_sync
(To Clock
Select Logic)
Figure 15-1
). The latch
/256, or

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