MCU AVR 16K FLASH 16MHZ 40-PDIP

ATMEGA16A-PU

Manufacturer Part NumberATMEGA16A-PU
DescriptionMCU AVR 16K FLASH 16MHZ 40-PDIP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA16A-PU datasheets
 


Specifications of ATMEGA16A-PU

Core ProcessorAVRCore Size8-Bit
Speed16MHzConnectivityI²C, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o32
Program Memory Size16KB (8K x 16)Program Memory TypeFLASH
Eeprom Size512 x 8Ram Size1K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case40-DIP (0.600", 15.24mm)Processor SeriesATMEGA16x
CoreAVR8Data Bus Width8 bit
Data Ram Size1 KBInterface Type2-Wire/SPI/USART
Maximum Clock Frequency16 MHzNumber Of Programmable I/os32
Number Of Timers3Maximum Operating Temperature+ 85 C
Mounting StyleThrough Hole3rd Party Development ToolsEWAVR, EWAVR-BL
Development Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKITMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitPackage40PDIP
Device CoreAVRFamily NameATmega
Maximum Speed16 MHzOperating Supply Voltage3.3|5 V
Controller Family/seriesAVR MEGANo. Of I/o's32
Eeprom Memory Size512ByteRam Memory Size1KB
Cpu Speed16MHzRohs CompliantYes
For Use WithATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KITLead Free Status / RoHS StatusLead free / RoHS Compliant
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Figure 24-7. Boundary-scan Cells for Oscillators and Clock Options
Table 24-4
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Table 24-4.
Enable Signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
Notes:
24.5.5
Scanning the Analog Comparator
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
8154B–AVR–07/09
XTAL1/TOSC1
To
Next
ShiftDR
Cell
EXTEST
0
1
0
D
Q
D
Q
1
G
From
ClockDR
UpdateDR
Previous
Cell
summaries the scan registers for the external clock pin XTAL1, Oscillators with
Scan Signals for the Oscillators
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TOSCK
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP Fuses are not
supported in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator
requiring internal capacitors to run unless the fuse is correctly programmed.
Figure 24-9
is attached to each of these signals. The signals are
Table
24-5.
ATmega16A
XTAL2/TOSC2
Oscillator
ShiftDR
ENABLE
OUTPUT
0
1
From
ClockDR
Previous
Cell
(1)(2)(3)
Scanned Clock Line
Clock Option
when not Used
External Clock
External Crystal
External Ceramic Resonator
External RC
Low Freq. External Crystal
32 kHz Timer Oscillator
To
Next
Cell
FF1
D
Q
0
0
1
0
0
Figure
24-8. The
239